; This is an example of sourcecode for the 65xxx and Z80 assembler made by ; Ruud Baltissen ; ; A file should begin with a Begin Address. May only bee preceeded by .EQ ; statements .ba $4000 ; These lines are valid for the Z80 and compatibles: .PZ80 ; Tells the assembler it is dealing ; with a Z80 /* ; the list of some undocumented z80 instructions... ; the missing SLL ($30-$37) shift instruction sll b sll c sll d sll e sll h sll l sll (hl) sll (ix+2) sll (iy) sll a ; shift a memory byte (pointed by IX,IY) and then load ; the result into a register rlc (ix)->b rlc (ix)->a sla (iy+10)->b sll (iy+10)->c sll (iy+10)->d sla (iy+10)->e sra (iy+10)->h sra (iy+10)->l rr (iy+10)->a rr (iy+10)->b rr (iy+10)->c rr (iy+10)->d rr (iy+10)->e ; set/reset the bit of a memory byte (pointed by IX,IY) and then ; load the result into a register set 3,(ix+2)->a set 4,(ix-1)->b set 5,(iy+100)->c set 6,(iy-100)->d set 7,(iy+1)->l res 0,(iy+1)->b res 7,(iy+1)->a set 0,(ix)->b set 7,(ix)->a set 3,(ix+11)->b ; using the 8 bit parts of the index registers (XL,XH,YL,YH) ; as a normal register ld xl,v0 ld yl,v1 ld xh,v2 ld yh,v3 adc a,xl adc a,xh adc a,yl adc a,yh add a,xl add a,xh add a,yl add a,yh sub xl sub xh sub yl sub yh sbc a,xl sbc a,xh sbc a,yl sbc a,yh and xl and xh and yl and yh xor xl xor xh xor yl xor yh or xl or xh or yl or yh cp xl cp xh cp yl cp yh inc xl inc xh inc yl inc yh dec xl dec xh dec yl dec yh ld xl,b ld xl,c ld xl,d ld xl,e ld xl,xl ld xl,xh ld xl,a ld xh,b ld xh,c ld xh,d ld xh,e ld xh,xl ld xh,xh ld xh,a ld yl,b ld yl,c ld yl,d ld yl,e ld yl,yl ld yl,yh ld yl,a ld yh,b ld yh,c ld yh,d ld yh,e ld yh,yl ld yh,yh ld yh,a ld b,xh ld b,xl ld b,yh ld b,yl ld c,xh ld c,xl ld c,yh ld c,yl ld d,xh ld d,xl ld d,yh ld d,yl ld e,xh ld e,xl ld e,yh ld e,yl ld a,xh ld a,xl ld a,yh ld a,yl ; end of z80 undocumented instructions list */ adc a,a ; 8F adc a,b ; 88 adc a,c ; 89 adc a,d ; 8A adc a,e ; 8B adc a,h ; 8C adc a,l ; 8D adc a,(hl) ; 8E adc a,(ix) ; DD 8E 00 adc a,(iy+$12) ; FD 8E 12 adc a,$12 ; CE 12 adc hl,bc ; ED 4A adc hl,de ; ED 5A adc hl,hl ; ED 6A adc hl,sp ; ED 7A add a,a ; 87 add a,b ; 80 add a,c ; 81 add a,d ; 82 add a,e ; 83 add a,h ; 84 add a,l ; 85 add a,(hl) ; 86 add a,(ix) ; DD 86 00 add a,(iy+$12) ; FD 86 12 add a,$12 ; C6 12 add hl,bc ; 09 add hl,de ; 19 add hl,hl ; 29 add hl,sp ; 39 add ix,bc ; DD 09 add ix,de ; DD 19 add ix,ix ; DD 29 add ix,sp ; DD 39 add iy,bc ; FD 09 add iy,de ; FD 19 add iy,iy ; FD 29 add iy,sp ; FD 39 and a ; A7 and b ; A0 and c ; A1 and d ; A2 and e ; A3 and h ; A4 and l ; A5 and (hl) ; A6 and (ix+$12) ; DD A6 12 and (iy) ; FD A6 00 and $12 ; E6 12 bit 0,(hl) ; CB 46 bit 1,(hl) ; CB 4E bit 2,(hl) ; CB 56 bit 3,(hl) ; CB 5E bit 4,(hl) ; CB 66 bit 5,(hl) ; CB 6E bit 6,(hl) ; CB 76 bit 7,(hl) ; CB 7E bit 0,(ix+$12) ; DD CB 12 46 bit 1,(ix+$12) ; DD CB 12 4E bit 2,(ix+$12) ; DD CB 12 56 bit 3,(ix+$12) ; DD CB 12 5E bit 4,(ix+$12) ; DD CB 12 66 bit 5,(ix+$12) ; DD CB 12 6E bit 6,(ix+$12) ; DD CB 12 76 bit 7,(ix+$12) ; DD CB 12 7E bit 0,(iy) ; FD CB 00 46 bit 1,(iy) ; FD CB 00 4E bit 2,(iy) ; FD CB 00 56 bit 3,(iy) ; FD CB 00 5E bit 4,(iy) ; FD CB 00 66 bit 5,(iy) ; FD CB 00 6E bit 6,(iy) ; FD CB 00 76 bit 7,(iy) ; FD CB 00 7E bit 0,a ; CB 47 bit 0,b ; CB 40 bit 0,c ; CB 41 bit 0,d ; CB 42 bit 0,e ; CB 43 bit 0,h ; CB 44 bit 0,l ; CB 45 bit 1,a ; CB 4F bit 1,b ; CB 48 bit 1,c ; CB 49 bit 1,d ; CB 4A bit 1,e ; CB 4B bit 1,h ; CB 4C bit 1,l ; CB 4D bit 2,a ; CB 57 bit 2,b ; CB 50 bit 2,c ; CB 51 bit 2,d ; CB 52 bit 2,e ; CB 53 bit 2,h ; CB 54 bit 2,l ; CB 55 bit 3,a ; CB 5F bit 3,b ; CB 58 bit 3,c ; CB 59 bit 3,d ; CB 5A bit 3,e ; CB 5B bit 3,h ; CB 5C bit 3,l ; CB 5D bit 4,a ; CB 67 bit 4,b ; CB 60 bit 4,c ; CB 61 bit 4,d ; CB 62 bit 4,e ; CB 63 bit 4,h ; CB 64 bit 4,l ; CB 65 bit 5,a ; CB 6F bit 5,b ; CB 68 bit 5,c ; CB 69 bit 5,d ; CB 6A bit 5,e ; CB 6B bit 5,h ; CB 6C bit 5,l ; CB 6D bit 6,a ; CB 77 bit 6,b ; CB 70 bit 6,c ; CB 71 bit 6,d ; CB 72 bit 6,e ; CB 73 bit 6,h ; CB 74 bit 6,l ; CB 75 bit 7,a ; CB 7F bit 7,b ; CB 78 bit 7,c ; CB 79 bit 7,d ; CB 7A bit 7,e ; CB 7B bit 7,h ; CB 7C bit 7,l ; CB 7D call nz,$3456 ; C4 56 34 call z,$3456 ; CC 56 34 call nc,$3456 ; D4 56 34 call c,$3456 ; DC 56 34 call po,$3456 ; E4 56 34 call pe,$3456 ; EC 56 34 call p,$3456 ; F4 56 34 call m,$3456 ; FC 56 34 call $3456 ; CD 56 34 ccf ; 3F cp a ; BF cp b ; B8 cp c ; B9 cp d ; BA cp e ; BB cp h ; BC cp l ; BD cp (hl) ; BE cp (ix) ; DD BE 00 cp (iy+$12) ; FD BE 12 cp $12 ; FE 12 cpd ; ED A9 cpdr ; ED B9 cpi ; ED A1 cpir ; ED B1 cpl ; 2F daa ; 27 dec a ; 3D dec b ; 05 dec c ; 0D dec d ; 15 dec e ; 1D dec h ; 25 dec l ; 2D dec (hl) ; 35 dec (ix) ; DD 35 00 dec (iy+$12) ; FD 35 12 dec bc ; 0B dec de ; 1B dec hl ; 2B dec sp ; 3B dec ix ; DD 2B dec iy ; FD 2B di ; F3 djnz * ; 10 FE ei ; FB ex (sp),hl ; E3 ex (sp),ix ; DD E3 ex (sp),iy ; FD E3 ex af,af' ; 08 ex de,hl ; EB exx ; D9 halt ; 76 im 0 ; ED 46 im 1 ; ED 56 im 2 ; ED 5E in a,($12) ; DB 12 in a,(c) ; ED 78 in b,(c) ; ED 40 in c,(c) ; ED 48 in d,(c) ; ED 50 in e,(c) ; ED 58 in h,(c) ; ED 60 in l,(c) ; ED 68 inc a ; 3C inc b ; 04 inc c ; 0C inc d ; 14 inc e ; 1C inc h ; 24 inc l ; 2C inc (hl) ; 34 inc (ix+$12) ; DD 34 12 inc (iy) ; FD 34 00 inc bc ; 03 inc de ; 13 inc hl ; 23 inc sp ; 33 inc ix ; DD 23 inc iy ; FD 23 ind ; ED AA indr ; ED BA ini ; ED A2 inir ; ED B2 jp (hl) ; E9 jp (ix) ; DD E9 jp (iy) ; FD E9 jp $3456 ; C3 56 34 jp nz,$3456 ; C2 56 34 jp z,$3456 ; CA 56 34 jp nc,$3456 ; D2 56 34 jp c,$3456 ; DA 56 34 jp po,$3456 ; E2 56 34 jp pe,$3456 ; EA 56 34 jp p,$3456 ; F2 56 34 jp m,$3456 ; FA 56 34 jr * ; 18 FE jr nz,* ; 20 FE jr z,* ; 28 FE jr nc,* ; 30 FE jr c,* ; 38 FE ld a,(hl) ; 7E ld b,(hl) ; 46 ld c,(hl) ; 4E ld d,(hl) ; 56 ld e,(hl) ; 5E ld h,(hl) ; 66 ld l,(hl) ; 6E ld a,(bc) ; 0A ld a,(de) ; 1A ld a,(ix+$12) ; DD 7E 12 ld b,(ix+$12) ; DD 46 12 ld c,(ix+$12) ; DD 4E 12 ld d,(ix+$12) ; DD 56 12 ld e,(ix+$12) ; DD 5E 12 ld h,(ix+$12) ; DD 66 12 ld l,(ix+$12) ; DD 6E 12 ld a,(iy+$12) ; FD 7E 12 ld b,(iy+$12) ; FD 46 12 ld c,(iy+$12) ; FD 4E 12 ld d,(iy+$12) ; FD 56 12 ld e,(iy+$12) ; FD 5E 12 ld h,(iy+$12) ; FD 66 12 ld l,(iy+$12) ; FD 6E 12 ld a,($3456) ; 3A 56 34 ld hl,($3456) ; 2A 56 34 *1 ld a,a ; 7F ld a,b ; 78 ld a,c ; 79 ld a,d ; 7A ld a,e ; 7B ld a,h ; 7C ld a,l ; 7D ld b,a ; 47 ld b,b ; 40 ld b,c ; 41 ld b,d ; 42 ld b,e ; 43 ld b,h ; 44 ld b,l ; 45 ld c,a ; 4F ld c,b ; 48 ld c,c ; 49 ld c,d ; 4A ld c,e ; 4B ld c,h ; 4C ld c,l ; 4D ld d,a ; 57 ld d,b ; 50 ld d,c ; 51 ld d,d ; 52 ld d,e ; 53 ld d,h ; 54 ld d,l ; 55 ld e,a ; 5F ld e,b ; 58 ld e,c ; 59 ld e,d ; 5A ld e,e ; 5B ld e,h ; 5C ld e,l ; 5D ld h,a ; 67 ld h,b ; 60 ld h,c ; 61 ld h,d ; 62 ld h,e ; 63 ld h,h ; 64 ld h,l ; 65 ld l,a ; 6F ld l,b ; 68 ld l,c ; 69 ld l,d ; 6A ld l,e ; 6B ld l,h ; 6C ld l,l ; 6D ld a,i ; ED 57 ld a,r ; ED 5F ld a,$12 ; 3E 12 ld b,$12 ; 06 12 ld c,$12 ; 0E 12 ld d,$12 ; 16 12 ld e,$12 ; 1E 12 ld h,$12 ; 26 12 ld l,$12 ; 2E 12 ld bc,$3456 ; 01 56 34 ld de,$3456 ; 11 56 34 ld hl,$3456 ; 21 56 34 ld sp,$3456 ; 31 56 34 ld bc,($3456) ; ED 4B 56 34 ld de,($3456) ; ED 5B 56 34 ; see *1 ld hl,($3456) ; ED 6B 56 34 ld sp,($3456) ; ED 7B 56 34 ld ix,($3456) ; DD 2A 56 34 ld ix,$3456 ; DD 21 56 34 ld iy,($3456) ; FD 2A 56 34 ld iy,$3456 ; FD 21 56 34 ld i,a ; ED 47 ld r,a ; ED 4F ld sp,hl ; F9 ld sp,ix ; DD F9 ld sp,iy ; FD F9 ld (bc),a ; 02 ld (de),a ; 12 ld (hl),a ; 77 ld (hl),b ; 70 ld (hl),c ; 71 ld (hl),d ; 72 ld (hl),e ; 73 ld (hl),h ; 74 ld (hl),l ; 75 ld (hl),$12 ; 36 12 ld (ix+$12),a ; DD 77 12 ld (ix+$12),b ; DD 70 12 ld (ix+$12),c ; DD 71 12 ld (ix+$12),d ; DD 72 12 ld (ix+$12),e ; DD 73 12 ld (ix+$12),h ; DD 74 12 ld (ix+$12),l ; DD 75 12 ld (ix+$12),$78 ; DD 36 12 78 ld (iy+$12),a ; FD 77 12 ld (iy+$12),b ; FD 70 12 ld (iy+$12),c ; FD 71 12 ld (iy+$12),d ; FD 72 12 ld (iy+$12),e ; FD 73 12 ld (iy+$12),h ; FD 74 12 ld (iy+$12),l ; FD 75 12 ld (iy+$12),$78 ; FD 36 12 78 ld ($3456),a ; 32 56 34 ld ($3456),hl ; 22 56 34 *2 ld ($3456),bc ; ED 43 56 34 ld ($3456),de ; ED 53 56 34 ; see *2 ld ($3456),hl ; ED 63 56 34 ld ($3456),sp ; ED 73 56 34 ld ($3456),ix ; DD 22 56 34 ld ($3456),iy ; FD 22 56 34 ldd ; ED A8 lddr ; ED B8 ldi ; ED A0 ldir ; ED B0 neg ; ED 44 nop ; 00 or a ; B7 or b ; B0 or c ; B1 or d ; B2 or e ; B3 or h ; B4 or l ; B5 or (hl) ; B6 or (ix+$12) ; DD B6 12 or (iy) ; FD B6 00 or $12 ; F6 12 otdr ; ED BB otir ; ED B3 out (c),a ; ED 79 out (c),b ; ED 41 out (c),c ; ED 49 out (c),d ; ED 51 out (c),e ; ED 59 out (c),h ; ED 61 out (c),l ; ED 69 out ($12),a ; D3 12 outd ; ED AB outi ; ED A3 pop af ; F1 pop bc ; C1 pop de ; D1 pop hl ; E1 pop ix ; DD E1 pop iy ; FD E1 push af ; F5 push bc ; C5 push de ; D5 push hl ; E5 push ix ; DD E5 push iy ; FD E5 res 0,a ; CB 87 res 0,b ; CB 80 res 0,c ; CB 81 res 0,d ; CB 82 res 0,e ; CB 83 res 0,h ; CB 84 res 0,l ; CB 85 res 1,a ; CB 8F res 1,b ; CB 88 res 1,c ; CB 89 res 1,d ; CB 8A res 1,e ; CB 8B res 1,h ; CB 8C res 1,l ; CB 8D res 2,a ; CB 97 res 2,b ; CB 90 res 2,c ; CB 91 res 2,d ; CB 92 res 2,e ; CB 93 res 2,h ; CB 94 res 2,l ; CB 95 res 3,a ; CB 9F res 3,b ; CB 98 res 3,c ; CB 99 res 3,d ; CB 9A res 3,e ; CB 9B res 3,h ; CB 9C res 3,l ; CB 9D res 4,a ; CB A7 res 4,b ; CB A0 res 4,c ; CB A1 res 4,d ; CB A2 res 4,e ; CB A3 res 4,h ; CB A4 res 4,l ; CB A5 res 5,a ; CB AF res 5,b ; CB A8 res 5,c ; CB A9 res 5,d ; CB AA res 5,e ; CB AB res 5,h ; CB AC res 5,l ; CB AD res 6,a ; CB B7 res 6,b ; CB B0 res 6,c ; CB B1 res 6,d ; CB B2 res 6,e ; CB B3 res 6,h ; CB B4 res 6,l ; CB B5 res 7,a ; CB BF res 7,b ; CB B8 res 7,c ; CB B9 res 7,d ; CB BA res 7,e ; CB BB res 7,h ; CB BC res 7,l ; CB BD res 0,(hl) ; CB 86 res 1,(hl) ; CB 8E res 2,(hl) ; CB 96 res 3,(hl) ; CB 9E res 4,(hl) ; CB A6 res 5,(hl) ; CB AE res 6,(hl) ; CB B6 res 7,(hl) ; CB BE res 0,(ix+$12) ; DD CB 12 86 res 1,(ix+$12) ; DD CB 12 8E res 2,(ix+$12) ; DD CB 12 96 res 3,(ix+$12) ; DD CB 12 9E res 4,(ix+$12) ; DD CB 12 A6 res 5,(ix+$12) ; DD CB 12 AE res 6,(ix+$12) ; DD CB 12 B6 res 7,(ix+$12) ; DD CB 12 BE res 0,(iy) ; FD CB 00 86 res 1,(iy) ; FD CB 00 8E res 2,(iy) ; FD CB 00 96 res 3,(iy) ; FD CB 00 9E res 4,(iy) ; FD CB 00 A6 res 5,(iy) ; FD CB 00 AE res 6,(iy) ; FD CB 00 B6 res 7,(iy) ; FD CB 00 BE ret ; C9 ret nz ; C0 ret z ; C8 ret nc ; D0 ret c ; D8 ret po ; E0 ret pe ; E8 ret p ; F0 ret m ; F8 reti ; ED 4D retn ; ED 45 rl a ; CB 17 rl b ; CB 10 rl c ; CB 11 rl d ; CB 12 rl e ; CB 13 rl h ; CB 14 rl l ; CB 15 rl (hl) ; CB 16 rl (ix+$12) ; DD CB 12 16 rl (iy) ; FD CB 00 16 rla ; 17 rlc a ; CB 07 rlc b ; CB 00 rlc c ; CB 01 rlc d ; CB 02 rlc e ; CB 03 rlc h ; CB 04 rlc l ; CB 05 rlc (hl) ; CB 06 rlc (ix+$12) ; DD CB 12 06 rlc (iy) ; FD CB 00 06 rlca ; 07 rld ; ED 6F rr a ; CB 1F rr b ; CB 18 rr c ; CB 19 rr d ; CB 1A rr e ; CB 1B rr h ; CB 1C rr l ; CB 1D rr (hl) ; CB 1E rr (ix+$12) ; DD CB 12 1E rr (iy) ; FD CB 00 1E rra ; 1F rrc a ; CB 0F rrc b ; CB 08 rrc c ; CB 09 rrc d ; CB 0A rrc e ; CB 0B rrc h ; CB 0C rrc l ; CB 0D rrc (hl) ; CB 0E rrc (ix+$12) ; DD CB 12 0E rrc (iy) ; FD CB 00 0E rrca ; 0F rrd ; ED 67 rst $00 ; C7 rst $08 ; CF rst $10 ; D7 rst $18 ; DF rst $20 ; E7 rst $28 ; EF rst $30 ; F7 rst $38 ; FF sbc a,a ; 9F sbc a,b ; 98 sbc a,c ; 99 sbc a,d ; 9A sbc a,e ; 9B sbc a,h ; 9C sbc a,l ; 9D sbc a,$12 ; DE 12 sbc a,(hl) ; 9E sbc a,(ix) ; DD 9E 00 sbc a,(iy+$12) ; FD 9E 12 sbc hl,bc ; ED 42 sbc hl,de ; ED 52 sbc hl,hl ; ED 62 sbc hl,sp ; ED 72 scf ; 37 set 0,a ; CB C7 set 0,b ; CB C0 set 0,c ; CB C1 set 0,d ; CB C2 set 0,e ; CB C3 set 0,h ; CB C4 set 0,l ; CB C5 set 1,a ; CB CF set 1,b ; CB C8 set 1,c ; CB C9 set 1,d ; CB CA set 1,e ; CB CB set 1,h ; CB CC set 1,l ; CB CD set 2,a ; CB D7 set 2,b ; CB D0 set 2,c ; CB D1 set 2,d ; CB D2 set 2,e ; CB D3 set 2,h ; CB D4 set 2,l ; CB D5 set 3,a ; CB DF set 3,b ; CB D8 set 3,c ; CB D9 set 3,d ; CB DA set 3,e ; CB DB set 3,h ; CB DC set 3,l ; CB DD set 4,a ; CB E7 set 4,b ; CB E0 set 4,c ; CB E1 set 4,d ; CB E2 set 4,e ; CB E3 set 4,h ; CB E4 set 4,l ; CB E5 set 5,a ; CB EF set 5,b ; CB E8 set 5,c ; CB E9 set 5,d ; CB EA set 5,e ; CB EB set 5,h ; CB EC set 5,l ; CB ED set 6,a ; CB F7 set 6,b ; CB F0 set 6,c ; CB F1 set 6,d ; CB F2 set 6,e ; CB F3 set 6,h ; CB F4 set 6,l ; CB F5 set 7,a ; CB FF set 7,b ; CB F8 set 7,c ; CB F9 set 7,d ; CB FA set 7,e ; CB FB set 7,h ; CB FC set 7,l ; CB FD set 0,(hl) ; CB C6 set 1,(hl) ; CB CE set 2,(hl) ; CB D6 set 3,(hl) ; CB DE set 4,(hl) ; CB E6 set 5,(hl) ; CB EE set 6,(hl) ; CB F6 set 7,(hl) ; CB FE set 0,(ix+$12) ; DD CB 12 C6 set 1,(ix+$12) ; DD CB 12 CE set 2,(ix+$12) ; DD CB 12 D6 set 3,(ix+$12) ; DD CB 12 DE set 4,(ix+$12) ; DD CB 12 E6 set 5,(ix+$12) ; DD CB 12 EE set 6,(ix+$12) ; DD CB 12 F6 set 7,(ix+$12) ; DD CB 12 FE set 0,(iy) ; FD CB 00 C6 set 1,(iy) ; FD CB 00 CE set 2,(iy) ; FD CB 00 D6 set 3,(iy) ; FD CB 00 DE set 4,(iy) ; FD CB 00 E6 set 5,(iy) ; FD CB 00 EE set 6,(iy) ; FD CB 00 F6 set 7,(iy) ; FD CB 00 FE sla a ; CB 27 sla b ; CB 20 sla c ; CB 21 sla d ; CB 22 sla e ; CB 23 sla h ; CB 24 sla l ; CB 25 sla (hl) ; CB 26 sla (ix+$12) ; DD CB 12 26 sla (iy) ; FD CB 00 26 sra a ; CB 2F sra b ; CB 28 sra c ; CB 29 sra d ; CB 2A sra e ; CB 2B sra h ; CB 2C sra l ; CB 2D sra (hl) ; CB 2E sra (ix+$12) ; DD CB 12 2E sra (iy) ; FD CB 00 2E srl a ; CB 3F srl b ; CB 38 srl c ; CB 39 srl d ; CB 3A srl e ; CB 3B srl h ; CB 3C srl l ; CB 3D srl (hl) ; CB 3E srl (ix+$12) ; DD CB 12 3E srl (iy) ; FD CB 00 3E sub a ; 97 sub b ; 90 sub c ; 91 sub d ; 92 sub e ; 93 sub h ; 94 sub l ; 95 sub $12 ; D6 12 sub (hl) ; 96 sub (ix) ; DD 96 00 sub (iy+$12) ; FD 96 12 xor a ; AF xor b ; A8 xor c ; A9 xor d ; AA xor e ; AB xor h ; AC xor l ; AD xor $12 ; EE 12 xor (hl) ; AE xor (ix) ; DD AE 00 xor (iy+$12) ; FD AE 12 ; These lines are valid for all 65xxx types: ; - 6502 ; - 65C02 ; - 65SC02 ; - 65SC802 ; - 65SC816 .ba $5000 .p6502 adc #$12 ; 69 12 adc $1234 ; 6D 34 12 adc $12 ; 65 12 adc $12,x ; 75 12 adc $1234,x ; 7D 34 12 adc $1234,y ; 79 34 12 adc ($12,x) ; 61 12 adc ($12),y ; 71 12 DummyLabel1 and #$12 ; 29 12 and $1234 ; 2D 34 12 and $12 ; 25 12 and $12,x ; 35 12 and $1234,x ; 3D 34 12 and $1234,y ; 39 34 12 and ($12,x) ; 21 12 and ($12),y ; 31 12 DummyLabel2 asl a asl a ; 0A asl ; 0A asl $1234 ; 0E 34 12 asl $12 ; 06 12 asl $12,x ; 16 12 asl $1234,x ; 1E 34 12 bcc * ; 90 FE bcs * ; B0 FE beq * ; F0 FE bit $1234 ; 2C 34 12 bit $12 ; 24 12 bmi * ; 30 FE bne * ; D0 FE bpl * ; 10 FE brk ; 00 bvc * ; 50 FE bvs * ; 70 FE clc ; 18 cld ; D8 cli ; 58 clv ; B8 cmp #$12 ; C9 12 cmp $1234 ; CD 34 12 cmp $12 ; C5 12 cmp $12,x ; D5 12 cmp $1234,x ; DD 34 12 cmp $1234,y ; D9 34 12 cmp ($12,x) ; C1 12 cmp ($12),y ; D1 12 cpx #$12 ; E0 12 cpx $1234 ; EC 34 12 cpx $12 ; E4 12 cpy #$12 ; C0 12 cpy $1234 ; CC 34 12 cpy $12 ; C4 12 dec $1234 ; CE 34 12 dec $12 ; C6 12 dec $12,x ; D6 12 dec $1234,x ; DE 34 12 dex ; CA dey ; 88 eor #$12 ; 49 12 eor $1234 ; 4D 34 12 eor $12 ; 45 12 eor $12,x ; 55 12 eor $1234,x ; 5D 34 12 eor $1234,y ; 59 34 12 eor ($12,x) ; 41 12 eor ($12),y ; 51 12 inc $1234 ; EE 34 12 inc $12 ; E6 12 inc $12,x ; F6 12 inc $1234,x ; FE 34 12 inx ; E8 iny ; C8 jmp $1234 ; 4C 34 12 jmp ($1234) ; 6C 34 12 jsr $1234 ; 20 34 12 lda #$12 ; A9 12 lda $1234 ; AD 34 12 lda $12 ; A5 12 lda $12,x ; B5 12 lda $1234,x ; BD 34 12 lda $1234,y ; B9 34 12 lda ($12,x) ; A1 12 lda ($12),y ; B1 12 ldx #$12 ; A2 12 ldx $1234 ; AE 34 12 ldx $12 ; A6 12 ldx $12,y ; B6 12 ldx $1234,y ; BE 34 12 ldy #$12 ; A0 12 ldy $1234 ; AC 34 12 ldy $12 ; A4 12 ldy $12,x ; B4 12 ldy $1234,x ; BC 34 12 lsr a ; 4A lsr ; 4A lsr $1234 ; 4E 34 12 lsr $12 ; 46 12 lsr $12,x ; 56 12 lsr $1234,x ; 5E 34 12 nop ; EA ora #$12 ; 09 12 ora $1234 ; 0D 34 12 ora $12 ; 05 12 ora $12,x ; 15 12 ora $1234,x ; 1D 34 12 ora $1234,y ; 19 34 12 ora ($12,x) ; 01 12 ora ($12),y ; 11 12 pha ; 48 php ; 08 pla ; 68 plp ; 28 rol a ; 2A rol ; 2A rol $1234 ; 2E 34 12 rol $12 ; 26 12 rol $12,x ; 36 12 rol $1234,x ; 3E 34 12 ror a ; 6A ror ; 6A ror $1234 ; 6E 34 12 ror $12 ; 66 12 ror $12,x ; 76 12 ror $1234,x ; 7E 34 12 rti ; 40 rts ; 60 sbc #$12 ; E9 12 sbc $1234 ; ED 34 12 sbc $12 ; E5 12 sbc $12,x ; F5 12 sbc $1234,x ; FD 34 12 sbc $1234,y ; F9 34 12 sbc ($12,x) ; E1 12 sbc ($12),y ; F1 12 sec ; 38 sed ; F8 sei ; 78 sta $1234 ; 8D 34 12 sta $12 ; 85 12 sta $12,x ; 95 12 sta $1234,x ; 9D 34 12 sta $1234,y ; 99 34 12 sta ($12,x) ; 81 12 sta ($12),y ; 91 12 stx $1234 ; 8E 34 12 stx $12 ; 86 12 stx $12,y ; 96 12 sty $1234 ; 8C 34 12 sty $12 ; 84 12 sty $12,x ; 94 12 tax ; AA tay ; A8 tsx ; BA txa ; 8A txs ; 9A tya ; 98 ; These lines are only valid for the 65C02 and 65SC02 .P65c02 bbr0 $12,* ; 0F 12 FD bbr1 $12,* ; 1F 12 FD bbr2 $12,* ; 2F 12 FD bbr3 $12,* ; 3F 12 FD bbr4 $12,* ; 4F 12 FD bbr5 $12,* ; 5F 12 FD bbr6 $12,* ; 6F 12 FD bbr7 $12,* ; 7F 12 FD bbs0 $12,* ; 8F 12 FD bbs1 $12,* ; 9F 12 FD bbs2 $12,* ; AF 12 FD bbs3 $12,* ; BF 12 FD bbs4 $12,* ; CF 12 FD bbs5 $12,* ; DF 12 FD bbs6 $12,* ; EF 12 FD bbs7 $12,* ; FF 12 FD rmb0 $12 ; 07 12 rmb1 $12 ; 17 12 rmb2 $12 ; 27 12 rmb3 $12 ; 37 12 rmb4 $12 ; 47 12 rmb5 $12 ; 57 12 rmb6 $12 ; 67 12 rmb7 $12 ; 77 12 smb0 $12 ; 87 12 smb1 $12 ; 97 12 smb2 $12 ; A7 12 smb3 $12 ; B7 12 smb4 $12 ; C7 12 smb5 $12 ; D7 12 smb6 $12 ; E7 12 smb7 $12 ; F7 12 ; These lines are valid for all types except the 6502 adc ($12) ; 72 12 and ($12) ; 32 12 bit #$12 ; 89 12 bit $12,x ; 34 12 bit $1234,x ; 3C 34 12 bra * ; 80 FE cmp ($12) ; D2 12 dec a ; 3A dec ; 3A eor ($12) ; 52 12 inc a ; 1A inc ; 1A jmp ($1234,x) ; 7C 34 12 lda ($12) ; B2 12 ora ($12) ; 12 12 phx ; DA phy ; 5A plx ; FA ply ; 7A sbc ($12) ; F2 12 sta ($12) ; 92 12 stz $1234 ; 9C 34 12 stz $12 ; 64 12 stz $12,x ; 74 12 stz $1234,x ; 9E 34 12 trb $1234 ; 1C 34 12 trb $12 ; 14 12 tsb $1234 ; 0C 34 12 tsb $12 ; 04 12 ; These lines are only valid for the 65802 and 65816 in Native mode .P65816_8 adc $12,S ; 63 12 adc ($12,S),Y ; 73 12 adc [$12] ; 67 12 adc [$12],Y ; 77 12 adc $123456 ; 6F 56 34 12 adc $123456,X ; 7F 56 34 12 and $12,S ; 23 12 and ($12,S),Y ; 33 12 and [$12] ; 27 12 and [$12],Y ; 37 12 and $123456 ; 2F 56 34 12 and $123456,X ; 3F 56 34 12 brk $12 ; 00 12 brl * ; 82 FD FF cmp $12,S ; C3 12 cmp ($12,S),Y ; D3 12 cmp [$12] ; C7 12 cmp [$12],Y ; D7 12 cmp $123456 ; CF 56 34 12 cmp $123456,X ; DF 56 34 12 cop $12 ; 02 12 eor $12,S ; 43 12 eor ($12,S),Y ; 53 12 eor [$12] ; 47 12 eor [$12],Y ; 57 12 eor $123456 ; 4F 56 34 12 eor $123456,X ; 5F 56 34 12 jml ($1234) ; DC 34 12 jsl $123456 ; 5C 56 34 12 jsr ($1234,x) ; FC 34 12 lda $12,S ; A3 12 lda ($12,S),Y ; B3 12 lda [$12] ; A7 12 lda [$12],Y ; B7 12 lda $123456 ; AF 56 34 12 lda $123456,X ; BF 56 34 12 mvn $12,$34 ; 54 34 12 mvp $12,$34 ; 44 34 12 ora $12,S ; 03 12 ora ($12,S),Y ; 13 12 ora [$12] ; 07 12 ora [$12],Y ; 17 12 ora $123456 ; 0F 56 34 12 ora $123456,X ; 1F 56 34 12 pea $1234 ; F4 34 12 pei ($12) ; D4 12 per * ; 62 FD FF phb ; 8B phd ; 0B phk ; 4B plb ; AB pld ; 2B rep #$12 ; C2 12 rtl ; 6B sbc $12,S ; E3 12 sbc ($12,S),Y ; F3 12 sbc [$12] ; E7 12 sbc [$12],Y ; F7 12 sbc $123456 ; EF 56 34 12 sbc $123456,X ; FF 56 34 12 sep #$12 ; E2 12 sta $12,S ; 83 12 sta ($12,S),Y ; 93 12 sta [$12] ; 87 12 sta [$12],Y ; 97 12 sta $123456 ; 8F 56 34 12 sta $123456,X ; 9F 56 34 12 stp ; DB tcd ; 5B tcs ; 1B tdc ; 7B tsc ; 3B txy ; 9B tyx ; BB wai ; CB xba ; EB xce ; FB ; These lines are only valid for the 16-bit modes .p65816_16 adc #$12 ; 69 12 00 adc #$1234 ; 69 34 12 and #$12 ; 29 12 00 and #$1234 ; 29 34 12 cmp #$12 ; C9 12 00 cmp #$1234 ; C9 34 12 cpx #$12 ; E0 12 00 cpx #$1234 ; E0 34 12 cpy #$12 ; C0 12 00 cpy #$1234 ; C0 34 12 eor #$12 ; 49 12 00 eor #$1234 ; 49 34 12 lda #$12 ; A9 12 00 lda #$1234 ; A9 34 12 ldx #$12 ; A2 12 00 ldx #$1234 ; A2 34 12 ldy #$12 ; A0 12 00 ldy #$1234 ; A0 34 12 ora #$12 ; 09 12 00 ora #$1234 ; 09 34 12 sbc #$12 ; E9 12 00 sbc #$1234 ; E9 34 12 ; Declaration of constants/variables .eq v0 = 100 .eq v1 = 200 .eq v2 = 255 .eq v3 = $88 ; Words smaller then 256 may be used as byte and bytes may be used as words .eq Byte = $55 ; defined as BYTE .eq Word = $00AA ; defined as WORD .eq Word2 = $00BB ; defined as WORD .eq LonB = $000033 ; byte defined as Long-address .eq LonW = $006633 ; word defined as Long-address .eq Long = $996633 ; Long-address .P6502 adc #Word ; 69 AA used as byte adc Byte,y ; 79 55 00 adc (Word,x) ; 61 AA used as byte adc (Word),y ; 71 AA used as byte and #Word ; 29 AA and Byte,y ; 39 55 00 used as word and (Word,x) ; 21 AA and (Word),y ; 31 AA cmp #Word ; C9 AA cmp Byte,y ; D9 55 00 cmp (Word,x) ; C1 AA cmp (Word),y ; D1 AA cpx #Word ; E0 AA cpy #Word ; C0 AA eor #Word ; 49 AA eor Byte,y ; 59 55 00 eor (Word,x) ; 41 AA eor (Word),y ; 51 AA jmp Byte ; 4C 55 00 jmp (Byte) ; 6C 55 00 jsr Byte ; 20 55 00 lda #Word ; A9 AA lda Byte,y ; B9 55 00 lda (Word,x) ; A1 AA lda (Word),y ; B1 AA ldx #Word ; A2 AA ldy #Word ; A0 AA ora #Word ; 09 AA ora Byte,y ; 19 55 00 ora (Word,x) ; 01 AA ora (Word),y ; 11 AA sbc #Word ; E9 AA sbc Byte,y ; F9 55 00 sbc (Word,x) ; E1 AA sbc (Word),y ; F1 AA sta Byte,y ; 99 55 00 sta (Word,x) ; 81 AA sta (Word),y ; 91 AA stx Word,y ; 96 AA sty Word,x ; 94 AA .P65C02 adc (Word) ; 72 AA and (Word) ; 32 AA bit #Word ; 89 AA cmp (Word) ; D2 AA eor (Word) ; 52 AA jmp (Byte,x) ; 7C 55 00 lda (Word) ; B2 AA ora (Word) ; 12 AA sbc (Word) ; F2 AA sta (Word) ; 92 AA ; This line is only valid for the 65802 and 65816 in Native mode .P65816_8 adc Word,S ; 63 AA adc (Word,S),Y ; 73 AA adc [Word] ; 67 AA adc [Word],Y ; 77 AA and Word,S ; 23 AA and (Word,S),Y ; 33 AA and [Word] ; 27 AA and [Word],Y ; 37 AA brk Word ; 00 AA cmp Word,S ; C3 AA cmp (Word,S),Y ; D3 AA cmp [Word] ; C7 AA cmp [Word],Y ; D7 AA cop Word ; 02 AA eor Word,S ; 43 AA eor (Word,S),Y ; 53 AA eor [Word] ; 47 AA eor [Word],Y ; 57 AA jml (Byte) ; DC 55 00 jsl Long ; 5C 33 66 99 jsr (Byte,x) ; FC 55 00 lda Word,S ; A3 AA lda (Word,S),Y ; B3 AA lda [Word] ; A7 AA lda [Word],Y ; B7 AA mvn Word,Word2 ; 54 BB AA mvp Word,Word2 ; 44 BB AA ora Word,S ; 03 AA ora (Word,S),Y ; 13 AA ora [Word] ; 07 AA ora [Word],Y ; 17 AA pea Byte ; F4 55 00 pei (Word) ; D4 AA rep #Word ; C2 AA sbc Word,S ; E3 AA sbc (Word,S),Y ; F3 AA sbc [Word] ; E7 AA sbc [Word],Y ; F7 AA sep #Word ; E2 AA sta Word,S ; 83 AA sta (Word,S),Y ; 93 AA sta [Word] ; 87 AA sta [Word],Y ; 97 AA /* The 658xx is able to address up 16 MB using a 24 bits address. Programs meant to be run within a 64 KB segment gain nothing when the Long-Address- mode is used. Worse, due to this LA-mode, they cannot be relocated to another segment. Therefor a way has to be found telling the assembler to use the LA-mode or the orignal 16-bits mode. My solution is to give all labels a 16 bits address unless they start with the code 'LA_' */ .ba $1425 Label1 LA_label1 .by 1, 2, 3, 4 adc Label1 ; 6D 25 14 adc Label1,X ; 7D 25 14 and Label1 ; 2D 25 14 and Label1,X ; 3D 25 14 cmp Label1 ; CD 25 14 cmp Label1,X ; DD 25 14 eor Label1 ; 4D 25 14 eor Label1,X ; 5D 25 14 lda Label1 ; AD 25 14 lda Label1,X ; BD 25 14 ora Label1 ; 0D 25 14 ora Label1,X ; 1D 25 14 sbc Label1 ; ED 25 14 sbc Label1,X ; FD 25 14 sta Label1 ; 8D 25 14 sta Label1,X ; 9D 25 14 adc LA_label1 ; 6F 25 14 00 adc LA_label1,X ; 7F 25 14 00 and LA_label1 ; 2F 25 14 00 and LA_label1,X ; 3F 25 14 00 cmp LA_label1 ; CF 25 14 00 cmp LA_label1,X ; DF 25 14 00 eor LA_label1 ; 4F 25 14 00 eor LA_label1,X ; 5F 25 14 00 lda LA_label1 ; AF 25 14 00 lda LA_label1,X ; BF 25 14 00 ora LA_label1 ; 0F 25 14 00 ora LA_label1,X ; 1F 25 14 00 sbc LA_label1 ; EF 25 14 00 sbc LA_label1,X ; FF 25 14 00 sta LA_label1 ; 8F 25 14 00 sta LA_label1,X ; 9F 25 14 00 ; Rest of file should always assemble with an original 6502: .P6502 ; Labels .eq q1 = 0 .eq q2 = 1 ; NEW: now it is allowed to alter EQ-labels (not advised, can make you ; loose track of the program) .eq q3 = 2 .eq q3 = 3 ; Predefined labels /* In the program some labels have been pre-defined for the user: P6502 P65C02 P65816_E P65816_8 P65816_16 P65816_M P65816_X Z80 These EQ-labels can be used in combination with the label CPU. CPU is altered by the directive .Pxxxxxx used for telling the assembler for which processor the file should be assembled. CPU can be used in combination with "conditional assembling" to in- or exclude certain parts of the file for assembling. Example: see further. */ ; you may use labels not known yet in the first pass .eq t1 = t2 + t3 ; nesting is allowed but cause extra passes = delay .eq t2 = t3 + t4 .eq t3 = t4 + t5 .eq t4 = t5 + t6 .eq t5 = 88 .eq t6 = 99 ; test the use of spaces and tabs .eq testline1 = $1 ; spaces .eq testline2 = $2 ; nothing .eq testline3 = $3 ; tabs .eq testline4 = $4 ; tabs .eq TeStLiNe5 = $5 ; labelnames should be case insensitive .eq testline6 = tEsTlInE5 + 1 .eq testline7 = "1" ; characters are allowed .eq testline8 = '"' ; character is quote ; These lines should give four the same operands in the bin file lda #"1" lda #'1' lda #$31 lda #49 ; Add/substract labels and values .eq v1 = $66 .eq v2 = $22 .eq v3 = v1 + v2 .eq v4 = v1 - v2 .eq v5 = v1 + v2 - $33 .eq v6 = v1 + v2 - $99 ; Result < 0 is allowed but ; v6 becomes WORD .eq v7 = (v1 - v2) ; arithmic '(' allowed .eq v8 = {v1 - v2} ; '{' is better because of use of ( ; by indirect commands .eq V9 = v1 + v1 + v1 ; Result > $FF -> WORD .eq a1 = $0010 ; WORD !!! .eq a2 = $10 ; BYTE !!! lda #v1 + v2 lda #(v1 + v2) lda #v1-v2 lda v1 + v2 lda v1-v2 lda v1 + v2 + $C0 ; > $FF, absolute lda a1 + v1 ; WORD lda #(v1 + v2) - v4 lda ((v1 + v2) + v2),y lda ((v1 + v2) + v2,x) lda ({v1 + v2} + v2),y lda ({v1 + v2} + v2,x) Start lda #$56 cmp #78 beq (Start + v2) ; arithmic '(' allowed beq {Start + v2} ; better is '{' lda v1 + (Start - v2) lda <(Word+3) sta data lda >(Word+3) sta data+1 jmp (data) jmp verder Data ; label may be used alone .by 0,0 .by a1 ; exception because a1 < $FF ; Fill a block with bytes .fb $EA, 8 .fb "B", 8 ; Fill a block with words .fw $EA, 8 .fw $1234, 8 .fw "A", 8 ; Fill a block with double-words .fd $12345678, 8 .fd 'X', 8 ; Text .tx "This is 'text' " .tx 'This is "text" as well ' Verder jmp move .rb $8000 ; assemble a PRG to be relocated later Move lda <(Verder) ldx >(Move) jmp Verder2 .re ; end of relocation Verder2 nop ; Conditional programming ; .CO displays the comment during the assembling .eq c0 = 0 .eq c1 = 1 .eq c2 = 1 .eq c3 = 1 .eq c4 = 1 .if c0 .by 1 .co This line should not be seen on screen !!! #1 .ei .if c1 .by 2 .co This line should be seen on screen as #1 !!! .ei .if c0 .by 3 .co This line should not be seen on screen !!! #2 .el .by 4 .co This line should be seen on screen as #2 !!! .ei .if c1 .by 5 .co This line should be seen on screen as #3 !!! .el .by 6 .co This line should not be seen on screen !!! #3 .ei .if c1 .by 7 .co This line should be seen on screen as #4 !!! .if c0 .by 8 .co This line should not be seen on screen !!! #3a .ei .el .by 9 .co This line should not be seen on screen !!! #4 .ei .if c0 .by 10 .co This line should not be seen on screen !!! #5 .if c1 .by 11 .co This line should not be seen on screen !!! #6 .ei .el .by 12 .co This line should be seen on screen as #5 !!! .ei .if c0 .by 13 .co This line should not be seen on screen !!! #7 .el .by 14 .co This line should be seen on screen as #6 !!! .if c1 .by 15 .co This line should be seen on screen as #7 !!! .ei .ei .if c1 .by 16 .co This line should be seen on screen as #8 !!! .if c2 .by 17 .co This line should be seen on screen as #9 !!! .if c3 .by 18 .co This line should be seen on screen as #10 !!! .if c4 .by 19 .co This line should be seen on screen as #11 !!! .el .by 20 .co This line should not be seen on screen !!! #8 .ei .el .by 21 .co This line should not be seen on screen !!! #9 .ei .el .by 22 .co This line should not be seen on screen !!! #10 .ei .el .by 23 .co This line should not be seen on screen !!! #11 .ei .if CPU = p6502 .co Assembling for original 6502 .ei .p65816_16 .if CPU = p65816_16 .co Assembling for 65816 16-bits Native mode .ei .if CPU = p65816_e .co This line should not be seen on screen !!! #12 .ei .P6502 jmp (data) jmp verder ; Branches and jumps sec bcs L_clc L_jsr1 jsr L_rts jmp L_jsr2 L_zf0 ldx #1 bne L_zf1 L_bmi dex bmi L_bpl .fb $EA, 10 ; 10 times $EA L_rts nop nop rts .fb $EA, 10 L_bpl inx bpl L_jmp L_zf1 dex beq L_bmi L_clc clc bcc L_zf0 L_jmp jmp L_jsr1 L_jsr2 jsr L_rts ; Test if assembler counts right. sec bcs L_7F .by $EA L_80 .fb $EA, $7E L_7F bcs L_80 ; A UNIX-like way to exclude large parts of text .co Discard large area /* MUST be first two characters... text text text .co This text must NOT be seen on screen !!! text text text */ again first two characters /* ... after tabs ... text text */ ... or spaces .co End of discarding large area ; Macros .ma mac1 lda &1 ldx &2 sta (&3),y sta &4 .me ; end of macro .ma mac0 lda #0 .me mac0 mac1 $01 #$23 $45 ($67,X) .co End of program /* ; these line MUST produce an error when placed BEFORE the remark flag .eq ttt1 = $55 + ; missing rest .eq ttt2 = $55 m ; wrong end .eq ttt3 = $55 , ; wrong end .by Start ; WORD lda #v1 + v2 + $C0 ; > $FF, error lda #(Start + v2) ; again lda (Start + v2) ; thinks it is a faulty indirect lda ((v1 + v2 + v2),y ; missing ')' lda ((v1 + v2 + v2,x) lda (v1 + v2 + v2)),y ; missing '(' lda (v1 + v2 + v2,x)) lda ($34,m) ; incorrect indirect lda ($34),m lda $34,m ; incorrect ZP lda $3456,m ; incorrect ABS ; Branch error sec bcs L_too_far .fb $EA, 130 L_too_far nop */ ; .EN tells the assembler that this is the last line to be assembled. All ; statememts after this line should be ignored. .en