IBM 5160 clone

What is it?

This is my own design of a clone of the well known IBM 5160 PC/XT.

State: Schematics and board.

DISCLAIMER

This design is based on various designs I found in manuals that I found on internet and in paper versions I have my self. There is no real PCB yet so I haven't be able to test anything at all.

Background

I always had a weak spot for the first IBM PC/XT computers and compatibles. But being a tinkerer I alway had the ideas to create my own design, one with improvements of course. My main ideas:
- Static RAM (SRAM) instead of Dynamic RAM (DRAM).
- 1 MB of RAM instead of the original 640 KB.
- An onboard Real Time Clock (RTC).

I have thought about replacing the keyboard circuit with a PS/2 compatible one but rejected that idea. Main reason: not original enough. But XT keyboards aren't easy to find anymore but there is a solution: the AT2XT keyboard converter.

Schematic and board

Static RAM

Using SRAM has two advantages:
- Less ICs needed because one IC is good for 512 KB.
- Using SRAM means I don't need memory refresh. This means that I can single-step through programs. If I would do this on a PC with DRAM, I would interrupt the refresh, the DRAM will loose its data and the whole PC would crash. Not needing refresh means the PC becomes a little faster as well.

1 MB of RAM

To cover 640 KB I will need at least two 512 KB IC and that on its turn means I will have 1 MB. Of the extra 384 KB I can use 320 KB for my own puposes. I need ROM as well and I reserved 64 KB for that. I could have both but for practical reasons, I would need extra I/O, it is why 64 KB of SRAM are missing.
The extra RAM can be used for UMB, for example. If you don't use EGA or VGA, 64 KB of RAM can be used to expand the 640 KB limit to 704 KB. Another use for the extra RAM is to use it as RAM-drive but you will need to write your own driver for it.

An onboard Real Time Clock

One thing a computer MUST have nowadays IMHO is a RTC. I still remember the days I did not have one and having various sets of floppies with data and source code and wondering: which one is the newest one ??? Thank God that changed when I got my first Multi-I/O card that included a RTC!
There is no typical XT RTC nor is there a typical I/O address dedicated to this RTC so I decided to use the DS12885, successor of the Motorola RTC used in the original IBM AT and used in many of its successors and many other computers. And as I/O address I want to use 070h as used by the IBM AT and, AFAIK, all newer PCs.

The main design

The base of my design is an Eagle schematic of a G2 PC/XT, an IBM PC/XT clone, that I made in the past. The advantage: much less work. The disadvantage: I have not a complete understanding how some things work. This is mainly the bottom part in the middle of the schematic around IC88, the 74LS175. I have studied it often enough because I needed to understand the working of some parts but not being essential knowledge, I forgot it later.

I stripped this design of DRAM, the EPROMs, refresh and parity circuit. Then I added seven ISA slots, 1 MB of SRAM, a RAM selection circuit, FlashRAM for the BIOS, a Turbo circuit and the Real Time Clock.

The RAM selection circuit

Having 1 MB of RAM, what to to do with the extra 384 KB? As said before, we loose 64 KB because I need some memory range for the BIOS = ROM. I use IC8, a 74154 4-to-16 demultiplexer, to split the upper 512 KB of the 8088's 1 MB memory range into 16 chunks of 32 KB each. IC87D, a 2-input AND gate, merges the two upper 32 KB ranges to create one 64 KB range for selecting IC5, a 128 KB FlashRAM (see later).
All other outputs of the 75154 are each connected to a DIP switch. The other ends are connected to a giant 14-input AND gate created out of IC7, a 74LS133 13-input AND gate, and IC87B, a 2-input AND gate. The output of the 133 is inverted by IC71F, a 74LS04, and selects IC6, the second 512 KB SRAM.
The DIP switches enable the user to enable or disable the upper 448 KB of memory in chunks of 32 KB. When not using any video or network card, theoretically it is possible to use all 448 KB of RAM for DOS.

128 KB of FlashRAM

The main reason I chose this type of ROM is quite simple: I have lot of them laying around. But having 128 KB of ROM available and only using 64 KB is a bit of a waste. So I started with adding jumpers, JP5, to input A16 so I could choose from two BIOSes at power-up.
During cleaning the original schematic from the parity check circuit, I noticed that I freed pin PB4 of the 8255. This pin clears the parity flipflop after a parity error has been detected. The idea rose to use this pin to select the second part of the FlashRAM in flight. This enables the user to select the second part of the ROM in flight! If needing only 8 to 16 KB for the BIOS, it means that 112 KB can be used as a ROM-disk, for example. Hmmm, what about using it as base for my PC-BOX project?
There is a risk that a program uses PB4 as it is meant to be used, clearing the parity flipflop, with the chance of crashing the computer. JP5 also gives you the possebility to discard this feature.

The Turbo circuit

The idea behind the Turbo circuit is to enable this board to run at 4.77 MHZ or at another speed. This other speed depends on the value of OSC1, an oscilator. In the schematic it has a value of 24 MHz which means that to 8088 will run at 8 MHz, when in Turbo mode.
The F/C input of IC1, an 8284, is (L), the processor will run at 4.77 MHz. This is the standard situation for an IBM PC, both the 5150 and 5160. If input F/C is pulled (H), the 8284 will use the clock fed to input EFI, divide it by three and feed it to the processor. OK, that sounds simple: the level at input F/C determines at what clock rate the processor will run. But from what I understood from various documents is that the transition has to be synchronized by the clocks. Another thing: when accessing a floppy drive, the clock has to be reduced to 4.77 MHz for the time being. As I understood that has to do with the controller IC on the floppy disk controller card. The combination of IC20A and IC20B, two 2-input OR gates, take car of that.
The "output" of 3-pin jumper JP1 determines at what speed the processor will run:
- no jumper at all means 4.77 MHz.
- a jumper from pin 2 to pin 3 means Turbo speed.
- a jumper from pin 1 to pin 2 means that output PB2 of the 8255 determines the speed. This gives the user the means to control the speed by software.
The output of IC20B is fed to IC3A, a 2-input NAND gate and fed to IC3C after inversion by IC3D. "No jumper" means that IC20B output a (H) that will result in a (L) for IC3C. The Data input of IC2B will become (H). Both inputs of IC3A become (H), resulting in a low Data input of IC2A. The OSC output of the 8284 is fed to IC2A, a 7474 D-flipflop, the output of OSC1 to IC2B.

The jumpers on the board

J1 : reset switch
J2 : ON = enable keyboard
J3 : ON = clear RAM of RTC
J5 : ON = no 8087 present

JP1: no jumper = 4.77 MHz
     1-2 = 8255 chooses mode by key = BIOS
     2-3 = turbo mode

JP2 and JP4 : choose 32 KB of RAM

JP5: 1-2 = choose high 64 KB of ROM
     2-3 = use 8255 to choose 64 KB of ROM
     2-4 = choose low 64 KB of ROM

Having questions or comment? You want more information?
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