RDY for the 65816

Some preliminary info

In 1997 I could obtain some other 65816s and started some experiments with them. I succeeded in letting my PETs, CBMs and VIC-20s run on the 65816.
The next experiment was upgrading a VIC-20 with an PC ISA bus. That went reasonably well but not perfect. One thing went absolutely wrong: the VIC-20 crashed the moment a negated the RDY line. And now I had to find out where things went wrong.

What went wrong?

Using a oscilloscope I soon found out: when negating RDY, the 65SC816 stopped outputting the address lines A16..23 to the data bus when CLK0 = (L). On its turn this meant that the halted data was clocked into the latch and not the address. A complete different address appeared and the VIC-20 crashed.

Solution

It simply means that we have to halt the latching of the address the moment RDY is active i.e. halt the clock that does that. And not only that, we have to be careful when we block the clock and when we release it again.

First some piece of important information: the 65SC816 can also be halted by keeping CLK0 (H) as long as you want. Controlling CLK0 means controlling the 65SC816. And deriving that latch-clock from CLK0 also means we control the latch.
The idea behind the solution is simple: the moment CLK0=(H) and RDY=(L), CLK will be kept (H) until both CLK and RDY are (H) again.

               +------+      +------+      +------+      +------+      +------+
CLK0           |      |      |      |      |      |      |      |      |      |
        -------+      +------+      +------+      +------+      +------+      +------

        -----------+             +-------+             +-------------+    +----------
RDY                |             |       |             |             |    |
                   +-------------+       +-------------+             +----+

               +--------------------+      +--------------------+      +------+
CLK            |                    |      |                    |      |      |
        -------+                    +------+                    +------+      +------
                   A                B             C    D             E    F

At point A RDY is pulled (L). Somewhere in time RDY is released, when is not important. What is important is that at the end of the phase that CLK0 = (H), RDY = (H) as well. This means that the CPU may continue.
At point C RDY is pulled (L) again but that has no consequences so far. But at the end of the next high CLK0 RDY is still (L) so CLK will be stretched again. In this case RDY is released again while CLK0 is still (L) but that has no consequences either. Only at point C is noticed that RDY is (H) again and the clock will be negated.
At point E RDY becomes (L) again and that is noticed. But a bit later RDY is raised again, before the falling edge of CLK0. The condition "CLK0=(H) and RDY=(L)" is met and nothing happens.

The problem is always: where to start? Let's find a stable situation first. To keep things simple I only used NAND gates, it meant I only needed two complete 74LS00 ICs.
IC2A inverts CLK0 and is fed to IC2B, which inverts it again. But pin 6 only follows the original CLK0 if input pin 5 is (H).
CLK0 and RDY are fed to IC1C. Its output is fed to IC1B. IC1B and IC1A together make a flipflop. The moment both CLK0 and RDY are (H), the flipflop will be reset at pin 5 and output 6 will become (H). Output pin 6 has been connected to pin 5 of IC2N. So as long as this pin 6 is (H), CLK will follow CLK0.

Now the special cases. First assume that CLK0 is (L). CLK0 is fed to both IC1C and IC1D. IC1D feeds the second set-input of the flipflop IC1A/IC1B. A (L) simply means that, whatever happens on the other inputs of IC1C and IC1D, nothing will happen with the flipflop. In short: the moment CLK0 is (L), nothing will happen at all!
CLK0 = (H) means that both NAND gates IC1C and IC1D are open for input. What will happen if RDY is (L)? We already figured out what will happen if CLK0 = (L): just nothing. The moment RDY is (L), the output of IC1D becomes (L) as well and the flipflop is reset.
RDY = (L) also causes pin 8 of IC1C to become (H) and thus pin 5 of IC1B as well. Because pin 4 is (H) as well, pin 6 of IC1B becomes (L) now. Pin 5 of IC2B becomes now (L) as well and causes output pin 6 to remain (H) as long as RDY stays (L).
Does RDY become (H) before CLK0 becomes (L)? Output pin 8 of IC1C becomes (L), reset the flipflop and IC2B will follow CLK0 again.

Second version

I call it a second version but in fact it is the same circuit but using some other parts. The advantage of this circuit is that

Creating PHI2

When creating my first project to replace a 6502 with a 65816, 6502 -> 65816, I noticed that some systems didn't react well when I connected PHI0 directly to PHI2 and needed a delay. Two 74F04 inverter gates worked fine. When creating other 65816 projects I decided to use a GAL to emulate the above circuits. Having two left over inputs and outputs I decided to use them for a possible delay. "Possible" because that is a matter of programming the GAL. I even went so far to put a resistor and a capacitor between an output and input to create an artificial delay, if needed. For an example please see: 6502 -> 65816.

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