8032-in-PC
What is it?
A PC ISA card that contains a 6502, some I/O, RAM and ROM. The PC acts as the terminal and drive station(s) for this "CBM 8032". For those who are not familar with the CBM 8032, it is a 6502 machine made by Commodore, some years older than the famous Commodore 64.State: Schematics and board.
Background
I can imagine that your first question is "WHY ISA ???". The ISA bus is obsolete and so why putting effort in such a thing? The answers are easy:- Older PCs, for example Commodore PCs like the PC20-II, are part of my hobby as well. So, A) I have enough of them and B) I can combine two CPUs in one project.
- Then why not PCI (-Express)? The answer is very simple: I have no idea how to do it for the PCI bus. It will most probably need a FPGA or another fancy IC and these are out of my scope. So ISA it is.
Roland Leurs created the ATOM-in-PC. To make a long story short, it inspired me to invent this "8032-in-PC".
The hardware
The "8032-in-PC" was not my first "in-PC" project. Some predecessors:- CP/M 3.0 for the PC
- 6502-in-PC
- 65816-in-PC
It may sound strange but this design is based on the 65816-in-PC. Just compare all boards and you will see what I mean. The main reason: this design is a bare 6502 machine without the MMU, a device that can be found on the 6502-in-PC.
The CBM 8032 has 18 KB of ROM on board:
- $B000 - $E7FF
- $F000 - $FFFF
The I/O normally ranges from $E800 to $EFFF but only $EC00 - $ECFF is used. The range $0000 - $8000 in a real CBM 8032 is 32 KB of RAM. Then you'll find video memory from $8000 - $87FFF and the range $9000 - $AFFF free to use for external ROMs. In this design all the ranges not covered by ROM or the 8255 are covered by RAM.
Keyboard and screen
It should be clear now that this system does not have its own keyboard and screen. So what about displaying text or reading the keyboard? The routines that send characters to the screen now send it to the 8255 together with some codes to tell the PC where to place it on its screen. The routine that reads the keyboards now asks the PC if a key has been pressed.Compatibility
Let's face it, this system is not 100% compatible and there are two main reasons:- This card does not contain all the 65xx ICs the original board has. That means that writing to or reading from any register of these ICs simply won't have any result. So programs doing that, most probably won't work and can maybe even crash.
- Writing to video memory won't have any result because there is no hardware that converts the data in the memory into a picture on the screen. I also don't have a routine that could check the memory and then informs the PC of the result because that will be a very time consuming process.
In short: any programm that doesn't access I/O or the video memory directly, should work.
The schematic
I'm going to use a GAL of course but staring at a GAL won't explain how it really works. So here is the IC version:
At the top-left you find the PC part: the ISA slot, the 74LS688 8-bit comparator, a DIP switch and a 8255. The 688 and DIP switch enables to select an address for the 8255. A reasonable good choice is $320.
The 8255 for the PC is connected to the 8255 for the 6502 part. The interconnections are straight: not only simple to draw in the schematic but also in the PCB. Four of the eight lines op port C have been connected to LEDs through a 7406 inverter. Main reason: to have some visible debug possibilities. Both 8255s are resetted by the PCs. IC10E, a 74LS04 inverter, inverts the signal and resets the 6502.
An oscillator generates the wanted clock frequency of your choice.
The RAM and ROM have been connected to the 6502 in a normal way, no weird details. The 8255, IC5, is an Intel IC and therefore needs a separate read (RD) and write (WR) line. These two are generated by IC3A, a 74LS139 2-to-4 demultiplexer. The 6502's R/W line determines which output, Y1 or Y3, becomes active but only if PHI2 is (H).
The biggest challenge is the selection of the RAM, ROM and I/O. IC7, a 74LS159 4-to-16 demultiplexer, is the base for generating the main CS signals for them. The 159 divides the upper 32 KB of 6502's 64 KB memory range in 16 blocks of 2 KB each.
Output 13 represents the range for the I/O, $E800-$EFFF and I need to find a safe range for the 8255. I first thought to keep it simple and to use the whole range but then I thought that it is possible to run into software addressing the original I/O directly and such an action could mess up the 8255. The CBM 8032 only uses the range $E800-$E881 AFAIU. That is not including possible mirror addresses. To keep the addressing simple this design will use the range $EC00-ECFF. This has been realised by ORing (IC14A) the inverted address line A10 (IC4A) with the output 13 and the result is fed to IC3A.
By tying the outputs 6 up to 15 together, with the exception of 13 of course, the base for selecting the ROM is created. This signal is called O159. But that is not all, I also copied a feature from 65816-in-PC: the abbility to write to RAM under the ROM and to disable the ROM so this RAM can be used. During a write the R/W signal is inverted using pin 5 of NAND IC12B, thus becoming (H), and ORed, IC14B, with signal O159 coming from the 159, in effect disabling O159. The output of the OR gate is sent to the ROM.
This signal is NANDed (IC12A) with the CS signal for the 8255. The effect is that the RAM is enabled at the moment that nor the ROM and neither the 8255 are selected.
The last feature is the ability to switch from ROM to RAM. The idea is simple: don't only disable the signal coming from output 13 of the 154 dring a write, but also disable it during a read. Therefore we need an I/O signal: PC7 of the 8255. This signal is fed to input 4 of NAND gate IC12B and disables the signal coming from output 13 of the 154 more permanent.
The GAL version
A small difference with the IC version: instead of connecting input RDY of the 6502 directly to +5V, I added a resistor. A two-pin header enables a user to halt the 6502 when needed.Schematic:
Board:
But then I ran into two small errors. The main reason: I thought I worked out the GAL equations but found out I had not. The first error was that I had forgotten to add a resistor to pull up the PC7 line to make sure the ROM can be activated after a reset. The second, quite minor error was that I assigned the wrong pin of the GAL to CS signal of the 8255. Luckily I was able to correct it by changing the equations.
I created a version 2 schematic and board that corrects these two errors but I won't publish them here. If anybody is interested, just email me.
The software
The ROM of this 8032 is based on the original ROM. In short: I went through the complete source code and replaced those parts that either addressed the original I/O or addressed the video memory. The replacing code tells the PC to execute, more or less, its equivalent.You can email me here.