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256 KB for your C64

What is it?

This is an expansion board that has to be placed on top of the motherboard of your C64 and enables you to use 256 KB of RAM, will give you some extra RAM, ROM and an IDE interface.

Remark: so far it is just an idea. The schematics and the designs of the PCBs have been created but the PCBs haven't been produced yet. And probably won't be. Main reason: my 6510 -> 65816 project for the Commodore 64.


In July 1987 the German magazine 64'er launched a project that enabled readers to upgrade their C64 up to 256 KB of RAM plus some extra ROM and/or RAM. The 256 KB of RAM was obtained by replacing the original eight 64 KB DRAMs with 256 KB ones like the 41256. This was possible because the 41256 has the same refresh mechanism as the 4164. This trick unfortunately can not be used for boards that use two 41464 DRAMs and that includes the "Small boards". The reasons: 1) 414256 DRAMs are bigger and don't fit in the sockets of a 41464 and 2), most important, 41464 will be refreshed by eight address lines but 414256s need to be refreshed on nine address lines. And there is no way to provide that nineth signal. A possible solution is replacing the two 41464 DRAMs with a PCB containing the eight 41256s.

To have this extra RAM and/or ROM, the VIC and SID were to be de-mirrored. What does that mean? The VIC occupies the memory range $D000-$D3FF and the SID $D400-D7FFF. But both only need 256 bytes (even less to be real) so the designer decided to free 3 * 356 bytes in each range. The freed ranges could be occupied by ROM and or RAM.
The 256 KB of RAM could be used to run four independent C64s in it. That included the video memory but then what about the color RAM? That had to be replaced as well with at least four 1024*4 bit of SRAM. 64'er kept it practical and used a 6264, 8K*8 SRAM, for the simple reason that this IC occupies less space than four 2114s.
Before switching to another bank/program, data of the momentary running program has to be saved. Think of the content of the various registers. This is what the extra RAM could be used for.
It is possible to use all 256 KB by one program but that means some common RAM is needed. This common RAM should include the Stack and BASIC variables for example. Two ranges have been reserved: $0000-$03FF and $C000-$C7FF. Each range can be active or not, independent of each other. Both ranges reside in the first bank.

I built it and it worked fine. But in one point I was disappointed: the promised software never came. OK, the question was if users could develop programs but AFAIK that never happened. I put it away as being a nice gadget and that was it for then.
Because of a renovation in my house, I had to move computers and boxes. One box fell and spoiled it contents. One item was the board I built over thirty years ago. Still having my 256 KB machine I decided to create a PCB instead of using the old board. Main reason: some wires got disconnected so I didn't trust it anymore. And if I'm going to create a new PCB, why not throw in some new ideas?

The original schematic

First a remark: this isn't the original design. For example it uses diodes and resistors to create some OR and AND gates. I never liked that so I replaced them with real TTL gates and did so already on my original board.
IC1, a 74LS138, is used to create two Chip Select lines out of the signals coming from IO2 (loose wire), R/W and the address line A5..7. IC27A, an NOR gate used as inverter creates the right level out of output Y6 for the clock input of the 74LS174 4-bit latch. The latch creates the extra address lines A16 and A17, needed to address the 256 KB, plus two signals to en- or disable the common areas.
Output Y7 of the 138 is used to read the settings of the four signals mentioned above plus reading another four inputs for personal use.

Special attention should be given to the reset/CLR line of the 174 latch. This input is pulled high by resistor R2 and is connected to jumpers J1 and J2. J1 can be used to connect a push-button to it, J2 to connect an on/off switch. By putting this switch in off position, a reset of the C64 won't change the momentary configuration and the C64 will start up with the same bank and common areas it was working with before te reset. Pushing the push-button when the on/off switch is "on" will reset the C64 including the board. Pushing the push-button when the on/off switch is "off" will only reset the latch but that can cause problems so do it only if you know what you are doing.

The 41256 has an extra multiplexed address line that needs to be fed with a 74LS257 or equivalent. The generated address line A16 and A17 are the two inputs for the inputs 1A and 1B. The output 1B is fed to input MA8 of all 41256s using a loose line. The A/B input is fed by tapping the signal from one of the other 74LS256s on the motherboard, again using u loose line.
The main idea is that the moment a common area has to be selected, the 74LS257 is to be disabled and the resistor pulls all the MA8 inputs (L) so the first bank is selected. IC4, another 138, plus two NOR gates, an OR gate in combination with some address lines and two enable signals for the two common areas create the needed signal for the 257. The idea is: the moment a common area is selected, the 257 is disabled and the 6510 will access the first bank.

IC16 is a socket that replaces a 74LS139 on the motherboard. This same 139, now placed on the PCB, creates the same signals and all but the ones originally meant for the SID and VIC, are fed back to the socket. The ones meant for the SID and VIC are each sent to another half of a 139 which creates the new signals for the SID and VIC and creates extra ones for the extra RAM and ROM. The new signals for the SID and VIC are fed back to IC16 as well. The signals for the RAM and ROM are combined using two 3-input AND gates and fed to the RAM and ROM itself.

Above IC16 you find the circuit where the 8 KB SRAMs relocates the original 2114 color RAM. Address line A16 and A17 make sure that the correct block of color RAM has been selected for the chosen bank.

My twists to the design

In 2023, 35 years later, I decided to make a new version and to implement some new ideas. In fact this is the fourth version but I decided not to bother you with the details of the previous versions.
  • The original design uses the last 32 bytes of the range of IO2, $DFE0-$DFFF, to select the active bank and to activate or de-activate the common ranges. 64'er claimed that this wouldn't be in the way of several hardware extensions using IO2 known to them. But that was over 30 years ago and a lot of new hardware has been created in the mean time. And I know that one of my own creations uses IO2 fully so IO2 was out of the question.
    Then what other range to use? The original design freed up six blocks of 256 bytes so why not using one of those blocks? But that will cost either RAM or ROM you may think but that will be covered by the next ideas.
  • The original design uses a 74LS175 4-bit data latch that latches two address lines and two data lines to set the number of the bank and to (dis)able the common RAM. Because of the two address lines the 175 occupies four addresses. A 541 8-bit data buffer reads those four lines mentioned earlier plus four bits that are pulled up by resistors and can be connected to four switches.
    These two ICs use together 40 pins on the PCB and the idea rose to replace them with a 40-pin 6821. The advantage: twenty I/O pins! OK, I need four for the banks and two for the common RAM but that leaves us 16 other pins. The idea: paged RAM and ROM.
  • Using paged RAM and ROM having pages of 768 bytes is a bit problematic: we either need some extra hardware or lose 256 of every 1024 bytes. Having pages of only 512 bytes is another solution. And that frees up another 256 bytes, so what to do with them? The idea rose to you use it for an 8-bit IDE interface. Not a 16-bit one because that would need extra hardware. I'm thinking of the one that I used in 1541IDE8. In contrary to hard disk drives, most Compact Flash cards have an 8 and 16-bit mode. Using it in 8-bit mode means you still have the full capacity of the card.
  • The 64'er used the original 2364 ROM and an EPROM, why not using just one EPROM instead? And why limiting the choice to three Kernals only? See later.
  • I decided to let the C64 start up with a custom Kernal that has only one function: let the user choose what Kernal and/or bank it will run or resume after a reset.
  • A simple thing but still. I don't like pull down resistors. So I don't like the resistor used to pull down all MA8 lines when the 257 is disabled. The oh so simple solution: replace the 257 with a 74LS157! When "disabled", its outputs become (L). problem solved! (Why didn't the original designer think of that?)
  • I have given it a good thought but I'm simply not interested in running four independent C64 systems in those 256 KB. What is the benefit of it? So I simply dropped this feature and therefore I didn't need the extra color RAM.

The schematic: the IC version

The main differences with the original design are quite visible, the 6522, the bigger ROM and no replacement of the color RAM anymore.
The 6522 takes care of: - Enabling the selection from up to eight different Kernals.
- Enabling the selection out of four pages of 512 bytes of RAM each.
- Enabling the selection out of 512 pages of 512 bytes of ROM each.
- Selecting one of the four 64 KB RAM banks on the C64.
- En- or disabling the two common areas.
Less visible: I replaced the 257 with a 157 as mentioned above.

The schematic: the GAL version

The board should plug into the original motherboard. The main reasons:
- we need to tap quite some signals
- we need to split up the I/O part
We divide the whole up in mainly three parts:
- The 6510 and IDE interface.
- The Kernal, extra RAM and extra ROM.
- The I/O.
The reason I have to split up has nothing to do with the design but with the board. First I had a big design with only one set of data lines. But the new EEPROMs and RAM received their data and address lines only from the socket of the original Kernal, IC13. The software now started to complain that I had to connect the data lines of the 6510 with those of the EEPROMs and RAM. A) that was not needed because that already happened on the motherboard, but B), more important, I had no place to draw the lines! So I divided the address and data lines in several blocks.

U2, 6510DEBUG, serves as one of the parts that that provides connection to the motherboard. It also provides signals like PHI2 and RESET.
U15, just an empty socket, is meant to replace the 74LS139 on the motherboard. IC7, could be the original 139, taps the signals from U15 and splits the original I/O signal up into the various signals as the original A15 would do. Only in this case the original VIC and SID signals are processed further. And this is done by IC8, another 139. Both original ranges are split up in four parts and of both ranges the lowest part is fed back to the original signals of the motherboard.
Two 2-input AND gates combine each two outputs of IC8A and IC8B and the resulting ranges are meant for the EEPROM and RAM.

IC4, a 74LS138, generates two signals that represent the ranges $Cxxx and $0xxx. With address line A11 the first ranges is limited to $C800-$CFFF and with A11 and an inverter the second range is limited to $0000-$07FF. Notice that the last range includes the video memory. These ranges are the "Common ranges". If needed these ranges are present all the time, independent what 64 KB RAM bank has been chosen. Whether a common range is activated or not, depends on two extra inputs, CA2 and CB2. See later. The resulting signals are mixed using an OR gate and its output is used to en- or disables the enable input of a 74LS157 DRAM multiplexer.

The 157 needs the signal A/B as input from the board and that is done by using a loose line. The resulting multiplexed signal has to be connected to the board as well using a loose line.
The choice of which one of the four banks has been chosen depends on two inputs: PB6 and PB7. Again, see later.

I wanted to have a choice out of eight different Kernals so I needed a replacement for the original 2364 KB ROM. That would mean a 27512 EPROM. But not having an EEPROM/FlashRAM equivalent, I went for the AM29F010. Not needing its whole capacitance I tied address line A16 to +5 Volt. The address lines A13..14 of the AM29F010 I connected to the signals PB0..2. Again, see later.

64'er only created 756 extra bytes of RAM and, using a jumper, two times 768 bytes of EPROM. I decided to have 4 pages of RAM and 512 pages of EEPROM, each page sized 512 bytes. The last feature enables you to have, for example, a ROM disk of 256 KB, my main reason for this choice.
So for the ROM I use nine 6821 I/O pins, for the RAM two.

The 6821 provides in the end all the signals I mentioned above. It has 20 I/O bits of which 18 can be configured as output. Two, CA1 and CB1, can be input only and have a function as well.
  • CA2 and CB2 select which common RAM is activated or de-activated: CA2 for lower area, CB2 for the higher one.
  • PB0..2 select the Kernal. With three bits we can have up to eight Kernals.
  • PA0..7 and PB3 select a 512-byte page of the 256 KB EEPROM.
  • PB4 and PB5 select a 512-byte page of a 2 KB SRAM.
  • PB6 and PB7 select the bank with 64 KB of DRAM.
As said, CA1 and CB1 have a use as well. (Remark: added later, not on the schematic) They are pulled high by resistors and can be negated by push-buttons connected to the 4-pin jumper block JP1. CA1 and CB1 can trigger an interrupt and for this reason outputs IRQA and IRQB have been connected to the IRQ input of the 6510. JP2 enables you to make a choice.
Where can they be used for? One idea is using one or both for a forced switching of the bank. But see later.

The reset line of the 6821 was given the same treatment as the 174 above.

The schematic, the GAL version

There are several differences with the IC version:
  • The 74LS138, NOR, OR and AND gates have been replaced by one GAL. Main reason: it saved some space and enabled me to change some ideas quite quickly.
  • Using a 20 pins IC for buffering only four lines seemed a bit of overkill to me. The only idea I could think of was using a 14-pin 74LS08 and using the four AND gates as buffer for each line.

The PCBs, the GAL version V3

Two versions, for the 250407 board and for the 250425 board:

The equations for the GALs, version V3

256KBV37.PLD for the 250407 board
256KBV35.PLD for the 250425 board

Software, or what can be done with it

For the original system there was software to run up to four different C64s in one go using time slashing. And so far as I then knew and still am convinced of, it was the only software written for this system. But then I asked myself: to what good? Most software that could make good use of the extra memory, like text editors or compilers, can be run much better on a much faster PC? No, as it looks now it will be just a freak hardware project for the moment until I, or someone else, writes some nice meaningful software for it.
The only things that come in my mind at the moment are an bigger version of BASIC (may be based ob the C128'S one) and Pascal. My own one or hacked version G-Pascal. Or maybe C?

-= Most probably not to be continued anymore. Replaced by 6510 -> 65816. =-

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