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256 KB for your C64

What is it?

This is an expansion board that has to be placed on your C64 and enables you to use 256 KB of RAM, will give you some extra RAM, ROM and an IDE interface. Software can enable you to run a program in each of the 64 KB of RAM completely indepent from each other.

Remark: so far it is just an idea, although a serious one. The schematics and the designs of the PCBs have been created but the PCBs haven't been produced yet.


In July 1987 the German magazine 64'er launched a project that enabled readers to upgrade their C64 up to 256 KB of RAM plus some extra ROM and/or RAM. To have this extra RAM and/or ROM the VIC and SID are -mirrored. What does that mean? The VIC occupies the memory range $D000-$D3FF and the SID $D400-D7FFF. But both only need 256 bytes (even less to be real) so the designer decided to free 3 * 356 bytes in each range. The freed ranges could be occupied by ROM and or RAM.
As said before: four independent C64s can run in those 256 KB of RAM. That icludes the video memory but what about the color RAM? That has to be replaced as well with at least four 1024*4 bit of SRAM. 64'er kept it practical and used a 6264, 8K*8 SRAM, for the simple reason that this IC occupies less space than four 2114s.
Before switching to another bank/program, data of the the momentary running program has to be saved. Think of the content of the various registers. This what the extra RAM can be used for.
It is possible to use all 256 KB by one program but that means some common RAM is needed. This common RAM should include the Stack and BASIC variables for example. Two ranges have been reserved: $0000-$3FFF amd $C000-$C7FF. Each range can be active or not, independent of each other. Both ranges reside in the first bank.

I built it and it worked fine. But in one point I was disappointed: the promised software never came. OK, the question was if users could develop programs but AFAIK that never happened.
Because of a renovation in my house I had to move computers and boxes. One box fell and spoiled it contents. One item was the board I built over thirty years ago. Still having my 256 KB machine I decided to create a PCB instead of using the old board. First reason: some wires got disconnected so I didn't trust it anymore. And if I'm going to create a new PCB, why bot throw in some new ideas?

The schematic of the original design

First: this is NOT the exact schematic of the original design. It is not complete and parts heve been replaced by other parts. 64'er used diodes and resistors to create an OR gate and two AND gates. I used IC32A, IC10A and IC10B in the schematic to clarify things. Bexause of using ICs, the original circuit for choosing between RAM and ROM is missing. The original Kernal ROM and a 27128 KB ROM plus a circuit to select the original and two extra Kernal ROMs are missing too. To obvious how that works IMHO.

The new ideas

  • The original design uses the last 32 bytes of the rang of IO2, $DFE0-$DFFF, to select the active bank and to acitvate or de-active the common ranges. 64'er claims that this won't be in the way of several hardwareb extensions using IO2 known to them. But that was over 30 years ago and a lot of new hardware has been created in the mean time. I know at least of one of my own creations using IO2 fully so IO2 was out of the question.
    Then what range to use? We just freed six blocks of 256 bytes so why not using one of those blocks? But that will cost either RAM or ROM you may think but that will be covered by the next ideas.
  • The original design uses a 74LS175 4-bit data latch that latches two address lines and two data lines to set the number of the bank and to (dis)able the common RAM. Because of the two address lines the 175 occupies four addresses. A 541 8-bit databuffer reads those four lines mentioned earlier plus four bits that are pulled up by resistors and can be connected to four swithes.
    These two ICs use together 40 pins on the PCB and the idea rose to replace them with a 40-pin 6821. The advantage: twenty I/O pins! OK, I need four for the banks and two for the common RAM but that leaves us 16 other pins. The idea: paged RAM and ROM.
  • Using paged RAM and ROM having pages of 768 bytes is a bit problematic: we either need some extra hardware or lose 256 of every 1024 bytes. Having pages of 512 bytes is another solution. And that frees up another 256 bytes, what to do with them? The idea rose to you use it for an 8-bit IDE interface. Not a 16-bit one because that would need extra hardware. I'm thinking of the one that I used in 1541IDE8. In contrary to hard disk drives, most Compact Flash cards have an 8 and 16-bit mode. Using it in 8-bit mode means you still have the full cpacity of the card.
  • Why using the original ROM and an EPROM, why not using one EPROM instead? And why limiting the choice to three Kernals only? See later.
  • How does the 64'er design switch from one task to another one? To be honest I still don't know exactly. But what I read was quite convincing.
  • 64'er said that the bank could be changed on flight to another one but I have my doubts. So the idea rose to let the C64 start up with a custon Kernal that has only one function: let the user choose what Kernal and/or bank it will run or resume after a reset.

The use of the extra bits

The 6821 has 20 I/O bits of which 18 can be configured as output. Two, CA1 and CB1, can be input only and have a function as well.
I was going for the idea of using extra ROM and extra RAM but how much of each? The idea was to have a lot of RAM so I could use it as a RAM disk. But that meant hardly no ROM. And after a power-up you have to fill this disk first and with what? Then a ROM disk sounded better. I ended up with this:
  • CA2 and CB2 select which common RAM is activated or de-activated: CA2 for lower bank, CB2 for the higher one.
  • PB0..2 select the Kernal. With three bits we can have up to eight Kernals.
  • PA0..7 and PB3 select a 512-byte page of a 256 KB EEPROM.
  • PB4 and PB5 select a 512-byte page of a 2 KB SRAM.
  • PB6 and PB7 select the bank with 64 KB of RAM.
As said, CA1 and CB1 have a use as well. They are pulled high by resistors and can be negated by push-buttons connected to the 4-pin jumper block JP1. CA1 and CB1 can trigger an interrupt and for this reason ouptputs IRQA and IRQB have been connected to either the NMI or IRQ input of the 6510. JP2 enables you to make a choice.
Where can they be used for? One idea is using one or both for a forced switching of the bank. But see later.

The schematic, part 1

  • The first thing you will see, or better, not: where are the 256 KB of RAM? Quite simple: replace all eight original 4164s with 41256s and connect all pins #1 with a line. The replacement of 4164s by 41256s is only possible because the 41256 has 16 pins, just like the 4164, and only needs to be refreshed by eight address lines.
  • This schematic can only be used for the older "Big boards" and then only those that use 4164 DRAMs. It can not be used for boards that use two 41464 DRAMs and that includes the "Small boards". The reasons: 1) 414256 DRAMs are bigger and don't fit in the sockets of a 41464 and 2), most important, 41464 will be refreshed by eight address lines but 414256s need to be refreshed on nine address lines. And there is no way to provide that nineth signal.
  • The board is meant to be plugged into the original C64 board. This is done by removing or desoldering the 6510 (U7), the color RAM (U6) and a 74LS139 (U15). The board will have these three ICs on the same place as the C64 board but instead of placing sockets in the holes, one should place pin extenders in them from the bottom side. The places of the original ICs should be filled with sockets. Then it is just a matter of sticking the extender pins in the corresponding sockets.
    There are several type of boards but so far I have created boards for the types 250425 and 250407.
  • At bottom-left of the schemati you will find IC4, a 74LS138 3-to-8 demultiplexer, that takes care of creating the common RAM ranges. IC27C, a 74LS27 3-input NOR gate mixes output Y0 of the 138 with address line A10 and PB6 (coming from the 6821) to generate a positive signal when the common range $0000-$03FF is chosen. IC27B does this with output Y6 and PB7 when the common range $C000-$07FF is chosen. IC32, a 2-input OR gate, mixes both signals and the result is fed to the enable input of IC3, a quad 2-to-1 multiplexer 74LS257. The moment a common range becomes active, all outputs are disabled. Resistor R1 makes sure that the first bank is chosen.
  • At the right of the 257 you find two 139s and DIL16. DIL16 is U15, the original 139, on the mother board. The original 139 can now be used as IC7. An added 139, IC8, creates the "reduced" VIC and SID signals plus the ones needed for the extra I/O, ROM and RAM. Outputs Y2 and Y3 of IC8A are combined using IC10A, a 2-input AND gate, to select the EEPROM and outputs Y2 and Y3 of IC8B are combined using IC10B to select the RAM.
  • IC1, the 6821, is selected by output Y1 of IC8A. With the exception of the reset line, all lines are connected to the C64 as to be expected. The reset input is pulled high by resistor R2 and is connected to jumpers J1 and J2. J1 can be used to connect a push-button to it. J2 to connect an on/off switch. By putting this switch in off position, a reset of the C64 won't change the momentary configuration and the C64 will start up with the bank and Kernal ROM it was working with before te reset. Pushing the push-button when the on/off switch is "on" will reset the C64 including the board. Pushing the push-button when the on/off switch is "off" will only reset the 6821 but that can cause problems so do it only if you know what you are doing.
  • On the right side of the 6821 you find the extra 256 KB of ROM and 2 KB of RAM already mentioned above.
  • Next to the RAM you find the IDE inteface. This interface only needs dat and addresslines, a reset line, some select lines and the Intel/Z80 read and write line. IC11, a 74LS245, buffers the data lines. IC12A, one half of a 74LS244, buffers the address lines and the reset line. IC9A, a 139, creates the two needed select lines. IC9B creates the needed read and write lines.
    LED1 provides means to see if the connected storage is in use. The other lines are not in use or have to be pulled up or low by resistors.
  • Above the extra ROM and RAM you find the extra Kernals. IC13 is not a real IC, it is needed to connect the PCB with the C64 motherboard. IC14 is an 128 KB FlasRAM/EEPROM but only 64 KB are used. I could use a 27512 EPROM but a FlashRAM is much easier to clear and to program. Certainly in the beginning, when I need to debug my start-up Kernal, this is a big advantage.
  • Top-right you find the color RAM. The used 6264 8 KB SRAM has three extra addres lines of which only two are needed. Address line A12 will not be used is connected to Vcc. A10 and A11 have been connected to PB6 and PB7. This ensures that when the 64 KB is switched the color RAM will be switched as well.

The schematic, part 2: the GAL version V2

There are several differences:
  • The NOR, OR and AND gates have been replaced by one GAL. Reason: it saved some space. Side remark: only after having designed the PCB it occured to me that I could have incorperated the 138 as well. If a revision is needed, I will do that.
  • Using a 20 pins IC for buffering only four lines seemed a bit of overkill to me. The only idea I could think of was using a 14-pin 74LS08 and using the four AND gates as buffer for each line.
  • In realty all address and data lines are connected to each other. But doing that in this design meant, for example, I had to connect the data pins of the 6510 with the ones of the extra RAM and ROM. That was unneeded because they already were connected with each other through the C64 motherboard. But most important, I needed the space for other lines. But the program for creating the PCB part kept nagging me to connect those pins with each other. So the only thing I could think of was creating separate blocks of data and address line.
  • I swapped various lines with each other, like some data and address lines of the color RAM part, for the simple reason that they needed not to be crossed in some way anymore on the PCB. Of course making sure that the behaviour of the whole design did not change.
  • I replaced resistor R1 that pulls pin 4 of the 257 down, with one that pulls the line up. TTL gates are not good in pulling signals up against resistors. And TTL inputs need much smaller values for pulling them Low than for pulling them High. The only difference will be that bank #3 will be the common bank and so far I haven't found any why that cannot work.

The schematic, part 2: the GAL version V3

Main change: the 138 has been incorperated into the GAL. Shown here is the version for the 250425 board. The only differences with the 250407 board is the way how various lines have been connected to the board. In case of the 250407 I had to move the GAL to be able to connect the various address lines at all and that caused a complete rerouting of almost all other lines which of course affected the schematic.

The PCBs, the GAL version V3

The equations for the GALs, version V3

256KBV37.PLD for the 250407 board
256KBV35.PLD for the 250425 board

Two other idea

What software is going to run on this hardware? I don't know yet and this the reason why it is a pure fun project so far. About multitasking first: it comes in handy if your PC is converting a a video into MP4 and you can do other things like writing a program and checking needed information on internet. The only time the editor program has to do something is when a key or combination of keys have been pressed. The rest of the time it is just sitting there doing "nothing". That time can be used to run the conversion of the video, one would think. But in case of this project the conversion of the video would stop the moment you would focus on the bank with the editor.
Does it mean then that it is impossible? I don't know. Let us assume we swith to the bank that runs the conversion and wait until a key is pressed. But there is a problem: switching bank means switching video memory as well. Which means on its turn that the video memory of the bank where the conversion is running, must be updated with data from the video memory of the bank where the editor is running. To be honest, I have no idea at all what programs I would like to run parallel to each others in those banks. But I could think of running an extended BASIC, Pascal or C in a system where a lot of memory is welcome and where I don't need four separate video memories.
So my idea: include the video memory in the common RAM. And that is just a matter of reprogramming the GAL.

The original desing uses $C000-$C7FFF as common area. When disabling the BASIC ROM, I prefer to have as much as RAM in one block as possible. So my idea: use $C800-$CFFFF as common RAM instead.


The 64'er came with software for switching the banks. That can not be used here because of the different I/O, 6821 versus 74LS175, but I will give it to you so you can have a look at it to see how it works. And maybe I will make an own version.

But for what can this hardware be used then? I haven't any idea yet so your ideas are welcome!

-= To be continued =-

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