Aster CT-80
What is it?
This page is dedicated to the Aster CT-80, a Dutch computer, compatible with the Radio Shack TRS-80 model 1 (TRS). The main reasons I'm interested in it is that:- I have two of them, many thanks to Fred Jan Kraan.
- It has been built using Eurocards.
- Schematics are available.
OK, no keyboards and no drives, but a keyboard can be made or emulated and drives can be found or replaced by Goteks.
Schematics
It appears that only ONE set survived and has been copied and copied over and over again. Most of the schematics are hand drawn, have hand drawn additions and the result is not something to be proud of. But they are good enough to start to draw new ones using Eagle in my case. For KiCad users: KiCad has a tool to convert Eagle into KiCad, so no worries here.CPU board
Three inverters of IC2, a 74LS240, generate the base clock. This can be 16 or 14.1926 MHz, depending on the crystal you use. 14.1926 MHz is needed if you want to remain TRS compatible. Using 16 MHz means you won't be able to read TRS cassettes and you will have troubles with executing original timing sensitive programs for the TRS. FYI: I don't own a TRS so a possible incompatibilty won't disturb me.
The clock is fed to IC16, a 74LS163 4-bit counter, that can be programmed to divide the speed by two or four. The final result is fed to the second half of IC13, a 74LS74 data flipflop, that divides the speed by two. To make sure that there is a good and fast rising edge of the resulting signal, transistor T1 is added.
Some I/O is needed to tell the 74LS163 to divide the clock by two or four. The Aster only supports a range of 256 bytes of I/O for the whole computer. So far I haven't read this anywhere in the documentation but I deduced this from the fact the CPU board only uses the address lines A0..7 and Z80 signal IORQ to generate an I/O address. IC10, a 74LS30 8-input NAND gate, creates the range $FC..$FF and outputs this signal towards to the bus as signal "I/O" on pin 30c and towards IC8, a 74LS155 2-to-4 demultiplexer. IC8 generates a signal when addressed $FE is accessed. This signal goes to the clock input, pin 11, of the second half of IC13. Data line D0 is fed to the data input and determines in the end what divisor is used.
The $FE signal is also fed to the clock input, pin 3, of the first half of IC11. This flipflop determines whether an active WAIT signal from the Z80 causes a NMI or not, using data line D4. If the HALT instruction is executed and the choice is not to generate a NMI, the Z80 won't do anything anymore and the only thing left to do to get the Aster going again, is to give it a reset.
Output Q of the flipflop is OR-ed (IC14A) with the WAIT signal. The output of IC14A is fed to NAND gate IC4A, together with a reset circuit (see later). Its output is fed to NOR gate IC15A, together with the signal coming from external NMI, inverted first by NOR gate IC15C, and its output triggers NMI.
The output of NAND gate IC4A is also fed to NOR gate IC15D (second input: see later) which on its turn clears the first half of flipflop IC11 if WAIT is activated. This means that the flipflop has to be set again if the next WAIT should trigger NMI again.
Another source for triggereing NMI is the combination R5 and C3. At power-up this RC combination causes a NMI. This RC combination can be connected to the main Reset input of the bus connector using resistor Rb. This means that a reset can cause a NMI as well.
At power-up the combination R6/C7 causes the Z80 to be resetted. By connecting the combination to the main Reset of the bus using resistor Ra, the Z80 can be resetted by an external reset.
The signal is first inverted using NAND gate IC4B. Its output is fed to NOR gate IC15D which on its turn also clears the first half of flipflop IC11. The output is also fed to IC15B which inverts the signal and triggers the RESET input of the Z80.
The Z80 generates the signals RD (read), WR (write), IREQ (I/O request) and MREQ (memory request). By combinig various signals, four OR gates (IC3) create four signals:
- RD = read from memory
- WR = write to memory
- IN = read from I/O
- OUT = write to I/O
Creating RAS, CAS and MUX.
To handle Dynamic RAM (DRAM), these three signals are needed and they are generated on this board. RAS is the simplest one, it is nothing else then MREQ outputted by the Z80.
CAS and MUX are generated by IC12, a 74LS74 D-flipflop. Both halves are clocked with the original clock of 16 or 14.1926 MHz. The CLeaR and Data input of the second half of IC12 and the CLear input of the first half are fed with a signal called MREQ but this is a signal generated by NAND gate IC4C with the Z80's outputs RD and WR as input. Personal opinion: it is quite confusing to give a signal NOT generated by the Z80 the same name as one of the signals outputted by this Z80.
The signal generated by output Q of the second half of IC12 is MUX. This signal is also fed to the Data input of the first half of IC12. The signal generated by output Q of this half of IC12 is RAS.
Remark: Z80 has an onboard address generator for refreshing DRAMs. The output RFSH (ReFreSH) signals the rest of the computer when this happens. But weird enough the TRS80, and therefore the Aster, don't use this signal. The question that remains: how is assured the all DRAM are refreshed?
Memory board
The board can either contain 16 or 64 KB of DRAM plus up to 14 KB of (EP)ROM. This amount is made out of a 2716 2K*8, a 2532 4K*8 and a 2564 8K*8. The 25xx types are rare and in the preliminary manual of the Aster there were already notes to replace the 2564 with a 2764. These three EPROMs are controlled by the 6331 PROM, which is an equivalent of the N82S123N.
The PROM itself is controlled by six lines:
- E2 = enable input: activated by the RAS signal = MREQ signal coming from the Z80.
- A0: (L) when an address in the first 8 KB of the memory range is selected.
- A1: (L) when an address in the range $2xxx or $8xxx is selected.
- A2: (L) when either (IC20a):
- The range $E000 is selected and
- Bit 3 of register $FE enables the BASIC ROM and
- Both address lines A10 and A11 are (H).
- The range $3000 is selected and
- Bit 3 of register $FE disables the BASIC ROM and
- Address line A11 is (L). or (IC25)
- The range $F000 is selected and
- Bit 3 of register $FE enables the BASIC ROM and
- Both address lines A10 and A11 are (L).
- A3: Bit 2 of IC26, the 74LS175 = whether there is or is not ROM available, (L) after a reset.
- A4: Bit 1 of IC26, the 74LS175 = status of the Boot ROM, whether it is or is not starting at $0000, (L) after a reset.
+---------------- 0 = Boot ROM at 0000 |+--------------- 0 = BASIC ROM is active ||+-------------- |||+------------- 0 = 2xxx or 8xxx ||||+------------ 0 = 0000-1FFF ||||| ||||| +-------- BASIC 0000-1FFF ROM ||||| | +----- BASIC 2000-2FFF ROM ||||| | | +-- BOOT ROM Addr B0 B2 Bt 1 2 3 00000 1 1 1 00001 1 1 1 00010 1 1 1 00011 1 1 0 Boot on 00100 1 1 1 00101 1 1 1 00110 1 1 0 Boot ROM on 0000-07FF (RESET) 00111 1 1 1 01000 1 1 1 01001 1 1 1 01010 1 1 1 01011 1 1 0 Boot ROM on 0000-07FF, BASIC* 01100 1 1 1 01101 1 1 1 01110 1 1 0 Boot ROM on 0000-07FF,BASIC*, addr 0000-0?FF 01111 1 1 1 10000 1 1 1 10001 1 1 1 10010 1 1 1 10011 1 1 0 Boot ROM on 3000-37FF 10100 1 1 1 10101 1 0 1 Basic ROM 2 active on 2000-2FFF 10100 0 1 1 Basic ROM 1 active on 0000-1FFF ?? 10101 1 1 1 10110 1 1 1 10111 1 1 1 11000 1 1 1 11001 1 1 1 11010 1 1 1 11011 1 1 0 Boot ROM on CPM, E000 - E7FF 11100 1 1 1 11101 1 1 1 11110 1 1 1 11111 1 1 1
How is the DRAM selected? RAS is nothing more than the Z80's MREQ signal so the RAS inputs of the DRAMs are always selected at every memory access, even when there is no RAM or ROM available. So we can ignore that.
The CAS signal for the DRAMs is generated by OR gate IC17a and it ors the CAS signal coming from the bus with the output signal from IC18, an 8-input NAND gate. To activate the output, all inputs should be (H):- 1: EPROM IC1 is not to be selected.
Video board
Floppy Disk Controller board
Cassette/keyboard board
Printer board
Serial interface board
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