The ISA bus
What is it
The ISA bus is the bus used in the IBM XT, AT, their clones and the successors of these machines. This document is meant for those people interested in, for example, my 6502 -> 65816 but aren't familiar with this bus.The pins
A1..31 B1..31
pin Signal I/O pin Signal I/O
A1 IOCHCK I B1 GND Ground
A2 SD7 I/O B2 RESET O
A3 SD6 I/O B3 +5 Vdc Power
A4 SD5 I/O B4 IRQ9 I
A5 SD4 I/O B5 -5 Vdc Power
A6 SD3 I/O B6 DRQ2 I
A7 SD2 I/O B7 -12 Vdc Power
A8 SD1 I/O B8 OWS I
A9 SD0 I/O B9 +12 Vdc Power
A10 IOCHRDY I B10 GND Ground
A11 AEN O B11 SMEMW O
A12 SA19 I/O B12 SMEMR O
A13 SA18 I/O B13 IOWR I/O
A14 SA17 I/O B14 IORD I/O
A15 SA16 I/O B15 DACK3 O
A16 SA15 I/O B16 DRQ3 I
A17 SA14 I/O B17 DACK1 O
A18 SA13 I/O B18 DRQ1 I
A19 SA12 I/O B19 REFRESH I/O
A20 SA11 I/O B20 CLK O
A21 SA10 I/O B21 IRQ7 I
A22 SA9 I/O B22 IRQ6 I
A23 SA8 I/O B23 IRQ5 I
A24 SA7 I/O B24 IRQ4 I
A25 SA6 I/O B25 IRQ3 I
A26 SA5 I/O B26 DACK2 O
A27 SA4 I/O B27 T/C O
A28 SA3 I/O B28 BALE O
A29 SA2 I/O B29 +5 Vdc Power
A30 SA1 I/O B30 OSC O
A31 SA0 I/O B31 GND Ground
C1-C18 D1-D18
pin Signal I/O pin Signal I/O
C1 SBHE I/O D1 MEMC16 I
C2 LA23 I/O D2 IOC16 I
C3 LA22 I/O D3 IRQ10 I
C4 LA21 I/O D4 IRQ11 I
C5 LA20 I/O D5 IRQ12 I
C6 LA19 I/O D6 IRQ15 I
C7 LA18 I/O D7 IRQ14 I
C8 LA17 I/O D8 DACK0 O
C9 MEMR I/O D9 DRQ0 I
C10 MEMW I/O D10 DACK5 O
C11 SD8 I/O D11 DRQ5 I
C12 SD9 I/O D12 DACK6 O
C13 SD10 I/O D13 DRQ6 I
C14 SD11 I/O D14 DACK7 O
C15 SD12 I/O D15 DRQ7 I
C16 SD13 I/O D16 +5 Vdc Power
C17 SD14 I/O D17 MASTER I
C18 SD15 I/O D18 GND Ground
Signal descriptions
SA0-A19 (I/O) Address bits 0 through 19 are used to address memory and I/O devices within the system. These 20 address lines, in addition to LA17 through LA23, allow access of up to 16Mb of memory. These signals are generated by microprocessor (CPU) or DMA controller.LA17-LA23 (I/O) These signals are used to address memory and I/O devices within the system. These signals are valid when "BALE" is high.
CLK (O) This is system clock. It is synchronous microprocessor cycle with 50% duty cycle. This signal should be used only for synchronisation.
RESET (O) This active (H) signal is used to reset or initialize system logic at power-up time.
SD0-SD15 (I/O) These signals provide data bus bits 0 through 15 for the microprocessor, memory, and I/O devices.
BALE (O) "Bus Address Latch Enable" is provided by the Bus controller and is used on system board to latch valid addresses. CPU address lines A0..19 are latched with falling edge of "BALE". "BALE" is forced high during DMA cycles.
IOCHCK (I) "I/O Channel Check", active (L), activates the NMI input of the CPU Mostly used to provide the system board with parity (error) information about memory or devices on the I/O channel.
IOCHRDY (I) "I/O channel ready", active (L), is used by devices to lengthen I/O or memory cycles. Any slow device using this line should drive it low immediately upon detecting its valid address and a READ or WRITE command. Machine cycles are extended by an integral number of clock cycles.
IRQ3..7, IRQ9..12, IRQ14..15 (I) Interrupt requests 3 through 7, 9..12 and 14..15 are used to signal microprocessor that an I/O device needs attention. The IRQs are prioritized, with IRQ0 having the highest priority and IRQ15 having the lowest priority. Active (H).
IORD (I/O) "I/O Read", active (L), instructs an I/O device to drive its data onto the data bus.
IOW (I/O) "I/O Write", active (L), instructs an I/O device to read the data on the data bus.
SMEMR (O) MEMR (I/O) These signals, active (L), instruct the memory devices to place data on the data bus to be read by the CPU. SMEMR is only active when an address the first 1 MB of memory is addressed. MEMR is active during all memory read cycles.
SMEMW (O) MEMW (I/O) Same as SMEMR and MEMR but then for writing data.
DRQ0..3 and DRQ5..7 (I) DMA Requests 0..3 and 5..7 are asynchronous channel requests used by peripheral devices and the I/O channel microprocessors to gain DMA services. They are prioritized, with DRQ0 having the highest priority, and DRQ7 having the lowest. They are active high, and they must be held high until the corresponding "DMA Request Acknowledge" (DACK) line goes active. DRQ0..3 will perform 8-bit transfers, DRQ5..7 will perform 16-bit transfers and DRQ4 is used on the system board and isn't available on the I/O channel.
DACK0..3 and DACK5..7 (O) "DMA Request Acknowledge", active (L), are used to acknowledge DMA requests (DRQ0-7).
AEN (O) "Address enable" signal is used to signal I/O whether the CPU, AEN = (L), or the DMA controller, AEN = (H), has control of the address bus, the data bus, IORD and IOWR.
REFRESH (I/O) This signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I/O channel.
T/C (O) "Terminal count" provides a pulse when the terminal count for any DMA channel is reached.
SBHE (I/O) "Bus high enable" indicates a transfer of data on the upper byte of data bus, D8-D15.
MASTER (I) This signal is used with DRQ line to gain control of the system. A processor or DMA controller on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DACK. Upon receiving the DACK, an I/O microprocessor may pull MASTER low, which will allow it to control the system address, data, and control lines.
MEMCS16 (I) "MEM 16 Chip Select", active (L), signals the system board if the present data transfer is a 1 wait state, 16-bit, memory cycle.
IOCS16 (I) "I/O 16 bit Chip Select", active (L), signals the system board if the present data transfer is a 1 wait state, 16-bit, I/O cycle.
OSC (O) "Oscillator", 14.381 MHz needed for the old CGA cards.
OWS (I) The "Zero Wait State" (OWS) signal tells the CPU that it can complete the present bus cycle without inserting any additional wait cycles.
I/O address map
Hex range I/O Device (commonly used) --------- -------------------------- 000-00F 8237 DMA controller 010-01F 8237 DMA controller #2 for PC-AT and better 020-02F 8259 Programmable Interrupt Controller, master 030-03F 8259 Programmable Interrupt Controller, slave for PC-AT 040-05F 8253 Programmable Interval Timer, 8254 for AT and better 060-06F Keyboard controller 070-07F Real Time Clock 080-083 DMA Page Register 170-177 AT hard disk (secondary) 1F0-1F8 AT hard disk 200-207 Game adapter (joystick A/D port) 220-22F SoundBlaster (compatible) sound card 278-27F Parallel printer port 3 2C0-2DF EGA #2 2E8-2EF Serial port 4 2F8-2FF Serial port 2 300-31F Prototype card 320-32F Hard disk (XT) 370-377 Diskette controller (secondary) 378-37F Parallel printer port 2 3B0-3BF Monochrome Graphic Adapter 3C0-3CF Enhanced Display Adapter (EGA/VGA) 3D0-3DF Color Graphics Adapter 3F0-3F7 Diskette controller 3E8-3EF Serial port 3 3F8-3FF Serial port 1
Use of the interrupts
IRQ0 System timer, generated by 8253/8254 timer IC
IRQ1 Keyboard
IRQ2 XT: ISA slot
AT: slave 8259
IRQ3 COM2 / COM4
IRQ4 COM1 / COM3
IRQ5 LPT2
IRQ6 Floppy Disk Controller
IRQ7 LPT1
IRQ8 Real Time Clock
IRQ9 Former IRQ2
IRQ10 Free
IRQ11 Free
IRQ12 Free
IRQ13 Coprocessor
IRQ14 Hard disk drive
IRQ15 Free
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