What is it?The Mini-V20 is a very small computer with as main components an 8088 or NEC V20 in minimum mode as CPU, 512 KB of SRAM, 128 KB of FlashRAM, a 16540 UART as its only I/O IC and one 8-bits ISA slot for expansion.
This is just an idea yet, PCB has been ordered.
BackgroundI am not only a Commodore fan but also a fan of (little) computers equiped with an 8088 or NEC V20, like the IBM PC/XT and its various clones, but also machines like the Multitech MPF-I/88. Unfortunately the prices on Ebay were way out of the range of what I wanted to pay for it. Building one myself was out of the question because I lacked some vital information like the BIOS.
Last year I found this French forum discussing this machine and they provided the needed information. So I designed a new PCB. Of course with some improvements like a lot more of RAM and ROM.
But then I realized that I still lacked a vital part: the keyboard. The PCB would not be a problem but the needed keys were a bit too expensive to my taste. So I decided to wait if this problem could be solved in some way.
In the mean time I ran into this little V20 machine: the V20-MBC. Very nice indeed. In fact I bought one. The only disadvantage of the V20-MBC was, IMHO, the lack of an ISA slot. But it inspired me to review my design of the MPF-I/88 and to turn it in a minimal system: no LCD screen, no keyboard and a 16540 UART for the needed exchange of data with the outside world.
The MPF-I/88 uses a 8088 as CPU. The reason why I call my design "Mini-V20" should be obvious: I want use a NEC V20 so that I can both run CP/M-80 and CP/M-86, just like the V20-MBC.
SchematicsThe design with logic gates instead of GALs
The design with GALs
The board of the above design
On forehand: bugs and other imperfections- Only when I received the PCB I noticed the types of the ICs are missing. So you have to look at the board to find out what IC is what.
- Busy writing the BIOS I noticed I had no idea how the interrupt was handled having no 8259 Interrupt Controller. At some point the 8088/V20 expects a vector on the bus. I found out that the MPF-I/88 solved this by pulling all data lines high using a 10K resistor array. And as you can see, in my schematic this array is missing. Practical solution: solder a 10-pins array to the bottom of IC7, the 74LS245, from pin 11 to 20 but skip pin 19. The result of this solution is that the processor reads 0FFh and wil execute "INT 0FFH".
Another idea that I have is piggybacking a 541 on top of the 245, connecting power and the pins 11 to 18. Its enable pins should be connected to the pin INTA of the processor. Its input pins should be connected to +5V. The advantage of this solution: it is a hard 0FFh that is read.
The above will be repaired in the future.
The hardwareAs said before, we use a V20 in minimu mode. This means we have to generate the memory an I/O signals IORD, IOWR, MEMR and MEMW ourself. I have been tempted to put the V20 in maximum mode and use a 8288 but this meant in the end that I needed an extra IC. I also decided to use GALs because that reduced the number of ICs and the size of the board significantly. But a schematic with GALs is hard to understand so let's have a look at the actual design with logic gates first.
This design only uses +5V and Ground. I decided to ommit +12V and -12V for the simpel reason that the only standard card that needs these power lines is a RS232 card. In case I have a real need for these power lines, my idea is to insert an expansion board with multiple ISA slots that also provides a connector for an AT power supply.
Address and data lines
The 8088/V20 has a multiplexed address and data bus. A 245 (IC12), a 541 (IC2) and two 573s (IC1 and IC11) take care of demultiplexing the signals. A datasheet of the 8088/V20 can explain how things exactly work.
IORD, IOWR, MEMR and MEMW
The 8088/V20 provides the signals RD, WR and IOM. IOM tells us if an I/O or memory operation is going on. WR and RD tell us if a write or read operation is going on. We first need to know if a write or read operation is going on at all and an AND gate, IC6a, takes care of that. Using the generated signal, RD and IOM a 139, IC14b, generates the needed signals.
With the MPF-I/88 you had only the possebility to choose one IRQ interrupt from the ISA slot and even then not all were available to choose from. The redesign left me with three free OR gates which, in combination with an 8 pins header, enabled me to select two fixed interrupts and to choose from three interruptd from the ISA slot and the the interrupt coming from the 16450. The GAL version even enables me to select all interrupt. That is why you don't see the header in this design.
The MPF-I/88 uses a NE555 timer to trigger the NMI interrupt. The main reason to do so is because of its keyboard. The Mini-V20 doesn't have a keyboard that needs to be checked regurlary so I connected the NMI input to the same pin from the ISA slot as in a PC: IOCHK.
The MPF-I/88 uses the IOCHK signal to tristate the CPU and the various buffers. So far I couldn't think of a valid reason to keep this feature so I decided to discard it and therefore the Mini-V20 cannot be tristated.
RAM and ROM
The original MPF-I/88 only had 24 KB of RAM and 48 KB of EPROM. I chose for 512 KB of RAM and 128 KB of FlashRAM. Of these 128 KB only 64 are visible. A jumper enabled the user to select which 64 KB part is visible. As an extra the part could also be selected using a free I/O pin.
Having no I/O any more I was afraid that I would loose this last feature. Then I found out about the output pins OUT1 and OUT2 of the UART and OUT2 now takes care of this feature.
Why not using some more RAM to fill the gap between the left by the first RAM and the ROM? Two reasons: I would need extra space for the extra RAM IC and the GAL has no left over output pins.
According the technical reference manual the MPF-I/88 runs at 4.77 MHz. To be honest, I really wonder how this frequency is generated out of 14.31 MHz using this 74107, IC10. This was my main reason to use an 8284 instead, the same IC as used by the IBM PC and its clones. The second reason: it enables me to run the Mini-V20 at 8 MHz (or maybe even at a faster speed?) at choice. A third reason: it simplifies the reset circuit.
Output OUT1 enables the user to select the speed by software. After a reset OUT1 is High and for that reason I invert this signal first, just to make sure that the Mini-V20 starts up at low speed. If an user wants the system to start up at high right from the start, it is just the matter of setting the correct jumper and/or telling the BIOS to pull OUT1 Low as soon as possible.
I can be very short about this: neither the MPF-I/88 nor the Mini-V20 have DMA capabilities and therefore all related pins of the ISA slot have been left unconnected.
This input of the ISA slot can halt the CPU temporary. The circuit of the MPF-I/88 is a bit simpler than the one of the IBM PC so I decided to use this one.
The BIOSI'm still working on it. It will be based on a BIOS that I use for various of my own XT clones. While working on it I had to take several decisions:
- The BIOS won't support any video card in the beginning.
How does that translate? Interrupt 10h normally handles all video operations. The original and this BIOS handles those functions where register AH ranges from AH = 00h up to AH = 0Fh. The original routines assume that there is a 6845 video IC on board that handles all video operations. But in case of the Mini-V20 the 6845 has been replaced, more or less, by this 16450 UART. So all routines had to be adjusted. Some routines cannot even be adjusted: function Ah = 0Ch writes a pixel to the screen and that is something a simple RS232 terminal cannot support. The function will return an error code in this case.
But I won't throw away the original routines, I just copy them to another part of the ROM. According to Dan Brown's Interrupt List function AH = 20h is not used by any known video function. I decided to reserve it for activating the original routines and to look for and to activate the ROM of a VGA card, if present.
- The BIOS won't support any keyboard as we know it. All involved routines handling the hardware will be replaced by ones where the 16450 UART will provide the bytes normally provided by the keyboard circuit. And it will be ASCII code that is provided, not the scan codes the original keyboard provided.
- I should be supporting Floppy Disk Drives (FDD) in some way but it won't be possible using the original Interrupt 13h routines. These routines are based upon using DMA to transfer data from and to the drives and the MINI-V20 does not support DMA.
I know it is possible to exchange data with a drive not using DMA. TIB-001-Cart is clone from the DD-001 cart for the Commodore 64 made by TIB using the GM82C765 IC which is nothing more than a more modern IC of the Zilog 765 used on the FDD controller cards made by IBM. If the 1 MHz 6510 of the C64 bcan handle 720 KB FDDs, why can't a V20 do the same?
- Then what about Hard Disk Drives (HDD)? AFAIK the original MFM and RLL cards use DMA as well. But AFAIK the XT-IDE card does not. This has to do with the fact that 16-bits data read from an IDE has to be split in two bytes first and, when writing data to an IDE drive, two bytes have to be merged to one word first. But if that is indeed the case, then XT-IDE maybe can be used as-is. We'll see....
The GALsThe GAL that generates mainly the I/O and memory signals, IC13:
Name -- I/O part of Mini-V20 --; Device G16V8AS; Designer Ruud Baltissen; Date 2021-05-12; Revision V0.1; Assembly --; Company --; Location --; Partno --; /* Define Logic Operators */ /* AND = & */ /* OR = # */ /* NOT = ! */ /* XOR = $ */ /* Define Input Pins */ pin 1 = GALCLK; /* clock input, not used */ pin 2 = FFNQ; /* /Q output of flipflop */ pin 3 = IOM; /* IO/M output of CPU */ pin 4 = WR; /* WR output of CPU */ pin 5 = RD; /* RD output of CPU */ pin 6 = A17; /* address line */ pin 7 = A18; /* address line */ pin 8 = A16; /* address line */ pin 9 = A19; /* address line */ pin 11 = GALOE; /* OE input, not used */ /* Define Output Pins */ pin 12 = RAM; /* */ pin 13 = IORD; /* */ pin 14 = IOWR; /* */ pin 15 = ROM; /* */ pin 16 = IO; /* */ pin 17 = MEMR; /* */ pin 18 = MEMW; /* */ pin 19 = FFDA; /* to data input of flipflop */ /* Boolean Equations */ MEMR = (WR & RD) # RD # IOM; MEMW = (WR & RD) # !RD # IOM; IORD = (WR & RD) # RD # !IOM; IOWR = (WR & RD) # !RD # !IOM; RAM = (MEMR & MEMW) # A19; ROM = (MEMR & MEMW) # !A19 # !A18 # !A17 # !A16; IO = !(IORD & IOWR); FFDA = (IORD & IOWR) # FFNQ;Comment: I have doubts if IO needs to be generated and used. Something that can be tested in the future and it won't hurt for the moment.
The GAl that mainly is used for ORring al interrupt signals, IC5:
Name -- description --; Device G16V8AS; Designer Ruud Baltissen; Date 2021-05-12; Revision V0.1; Assembly --; Company --; Location --; Partno --; /* Define Logic Operators */ /* AND = & */ /* OR = # */ /* NOT = ! */ /* XOR = $ */ /* Define Input Pins */ pin 1 = GALCLK; /* clock input, not used */ pin 2 = IRQU; /* interrupt coming from UART */ pin 3 = CLK; /* clock coming from 8284 */ pin 4 = IRQ5; /* */ pin 5 = IRQ4; /* */ pin 6 = IRQ3; /* */ pin 7 = IRQ6; /* */ pin 8 = IRQ7; /* */ pin 9 = IRQ2; /* */ pin 11 = GALOE; /* OE input, not used */ pin 12 = IOCHK; /* */ pin 18 = OUT1; /* coming from 16450 UART */ /* Define Output Pins */ pin 13 = SPEED; /* to speed selct jumpers */ pin 14 = NMI; /* to CPU */ pin 15 = INTR; /* to CPU */ pin 19 = FFCLK; /* to CLK input of flipflop */ /* Boolean Equations */ SPEED = !OUT1; NMI = !IOCHK; FFCLK = !CLK; INTR = IRQ2 # IRQ3 # IRQ4 # IRQ5 # IRQ6 # IRQ7 # IRQU;Comments:
- I wonder if the inversion of CLK is needed. This is something that can be tested quite easily here.
- Don't connect resistor #7 of the array RN1 to CLK. I used the array out of convenience. Just cut its pin before placing the array on the board.
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