The PC-1 - bus

What is it

The PC-1 - bus is the bus used by the Commodore PC-1. The PC-1 is a small PC with just one 360 KB drive and all devices integrated on the motherboard. Being very small, it has no internal PC slots but an external expansion bus. I wanted to add some extra connectors to this bus so I could add extra memory and an hard disk drive.

Then I found out that the expansion bus only has 60 pins. And this simply means it isn't ISA bus compatible. Having no schematic or manuals, making an adapor didn't seem to be simple. But I was very lucky to be given an external hard disk for this PC1. It appeared to be nothing more then a metal box containg a power supply, a Seagate ST-225 20 MB disk, an Omti controller and a flatcable connecting the card with the expansion bus. And this flatcable was my stone of Rosetta!

The pins

Signals seen from RIGHT to LEFT at the back of the computer !!!

top row                   bottom row                        
pin  Signal   I/O         pin  Signal  I/O            

1    GND      Ground      2    SD7     I/O
3    RESET    O           4    SD6     I/O
5    GND      Ground      6    SD5     I/O
7    IRQ2     I           8    SD4     I/O
9    GND      Ground      10   SD3     I/O
11   DRQ2     I           12   SD2     I/O
13   GND      Ground      14   SD1     I/O
15   GND      Ground      16   SD0     I/O
17   IOCHCK   I           18   IOCHRDY I
19   GND      Ground      20   AEN     O
21   MEMW     O           22   SA19    I/O
23   MEMR     O           24   SA18    I/O
25   IOWR     I/O         26   SA17    I/O
27   IORD     I/O         28   SA16    I/O
29   DACK3    O           30   SA15    I/O
31   DRQ3     I           32   SA14    I/O
33   DACK1    O           34   SA13    I/O
35   DRQ1     I           36   SA12    I/O
37   REFRESH  I/O         38   SA11    I/O
39   CLK      O           40   SA10    I/O
41   IRQ7     I           42   SA9     I/O
43   IRQ6     I           44   SA8     I/O
45   IRQ5     I           46   SA7     I/O
47   IRQ4     I           48   SA6     I/O
49   IRQ3     I           50   SA5     I/O
51   DACK2    O           52   SA4     I/O
53   T/C      O           54   SA3     I/O
55   BALE     O           56   SA2     I/O
57   GND      Ground      58   SA1     I/O
59   OSC      O           60   SA0     I/O

Signal descriptions

SA0-A19 (I/O) Address bits 0 through 19 are used to address memory and I/O devices within the system. These 20 address lines, in addition to LA17 through LA23, allow access of up to 16Mb of memory. These signals are generated by microprocessor (CPU) or DMA controller.

CLK (O) This is system clock. It is synchronous microprocessor cycle with 50% duty cycle. This signal should be used only for synchronisation.

RESET (O) This active (H) signal is used to reset or initialize system logic at power-up time.

SD0-SD7 (I/O) These signals provide data bus bits 0 through 7 for the microprocessor, memory, and I/O devices.

BALE (O) "Bus Address Latch Enable" is provided by the Bus controller and is used on system board to latch valid addresses. CPU address lines A0..19 are latched with falling edge of "BALE". "BALE" is forced high during DMA cycles.

IOCHCK (I) "I/O Channel Check", active (L), activates the NMI input of the CPU Mostly used to provide the system board with parity (error) information about memory or devices on the I/O channel.

IOCHRDY (I) "I/O channel ready", active (L), is used by devices to lengthen I/O or memory cycles. Any slow device using this line should drive it low immediately upon detecting its valid address and a READ or WRITE command. Machine cycles are extended by an integral number of clock cycles.

IRQ2..7 (I) Interrupt requests 3 through 7, 9..12 and 14..15 are used to signal microprocessor that an I/O device needs attention. The IRQ's are prioritised, with IRQ0 having the highest priority and IRQ15 having the lowest priority. Active (H).

IORD (I/O) "I/O Read", active (L), instructs an I/O device to drive its data onto the data bus.

IOW (I/O) "I/O Write", active (L), instructs an I/O device to read the data on the data bus.

MEMR (I/O) This signal, active (L), instructs the memory devices to place data on the data bus to be read by the CPU.

MEMW (I/O) Same as MEMR but then for writing data.

DRQ0..3 (I) DMA Requests 0..3 are asynchronous channel requests used by peripheral devices and the I/O channel microprocessors to gain DMA services. They are prioritised, with DRQ0 having the highest priority, and DRQ3 having the lowest. They are active high, and they must be held high until the corresponding "DMA Request Acknowledge" (DACK) line goes active.

DACK0..3 (O) "DMA Request Acknowledge", active (L), are used to acknowledge DMA requests (DRQ0..3).

AEN (O) "Address enable" signal is used to signal I/O whether the CPU, AEN = (L), or the DMA-controller, AEN = (H), has control of the address bus, the data-bus, IORD and IOWR.

REFRESH (I/O) This signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I/O channel.

T/C (O) "Terminal count" provides a pulse when the terminal count for any DMA channel is reached.

OSC (O) "Oscillator", 14.381 MHz needed for the old CGA-cards.

Remarks:
- The signal "Card Select" is missing.
- Except Ground, all other power signals are missing as well.
- Compared to the ISA bus, the pins of the top row have been shifted one pin to the right.

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